diff mbox series

[25/65] drm/i915: pass dev_priv explicitly to DSPARB

Message ID 9e8dc8978ce3122a0e9c53778be547875a9ae6d8.1717514638.git.jani.nikula@intel.com (mailing list archive)
State New, archived
Headers show
Series drm/i915: finish the job of removing implicit dev_priv | expand

Commit Message

Jani Nikula June 4, 2024, 3:25 p.m. UTC 
Avoid the implicit dev_priv local variable use, and pass dev_priv
explicitly to the DSPARB register macro.

Signed-off-by: Jani Nikula <jani.nikula@intel.com>
---
 drivers/gpu/drm/i915/display/i9xx_wm.c | 22 ++++++++++++----------
 drivers/gpu/drm/i915/i915_reg.h        |  2 +-
 drivers/gpu/drm/i915/i915_suspend.c    |  6 ++++--
 3 files changed, 17 insertions(+), 13 deletions(-)

Comments

Rodrigo Vivi June 6, 2024, 3:47 p.m. UTC | #1 
On Tue, Jun 04, 2024 at 06:25:43PM +0300, Jani Nikula wrote:
> Avoid the implicit dev_priv local variable use, and pass dev_priv
> explicitly to the DSPARB register macro.

Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> 
> Signed-off-by: Jani Nikula <jani.nikula@intel.com>
> ---
>  drivers/gpu/drm/i915/display/i9xx_wm.c | 22 ++++++++++++----------
>  drivers/gpu/drm/i915/i915_reg.h        |  2 +-
>  drivers/gpu/drm/i915/i915_suspend.c    |  6 ++++--
>  3 files changed, 17 insertions(+), 13 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
> index 628e7192ebc9..fd14010b4cc3 100644
> --- a/drivers/gpu/drm/i915/display/i9xx_wm.c
> +++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
> @@ -269,13 +269,15 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
>  
>  	switch (pipe) {
>  	case PIPE_A:
> -		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +		dsparb = intel_uncore_read(&dev_priv->uncore,
> +					   DSPARB(dev_priv));
>  		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
>  		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
>  		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
>  		break;
>  	case PIPE_B:
> -		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +		dsparb = intel_uncore_read(&dev_priv->uncore,
> +					   DSPARB(dev_priv));
>  		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
>  		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
>  		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
> @@ -300,7 +302,7 @@ static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
>  static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
>  			      enum i9xx_plane_id i9xx_plane)
>  {
> -	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
>  	int size;
>  
>  	size = dsparb & 0x7f;
> @@ -316,7 +318,7 @@ static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
>  static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
>  			      enum i9xx_plane_id i9xx_plane)
>  {
> -	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
>  	int size;
>  
>  	size = dsparb & 0x1ff;
> @@ -333,7 +335,7 @@ static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
>  static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
>  			      enum i9xx_plane_id i9xx_plane)
>  {
> -	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
> +	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
>  	int size;
>  
>  	size = dsparb & 0x7f;
> @@ -1787,7 +1789,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  
>  	switch (crtc->pipe) {
>  	case PIPE_A:
> -		dsparb = intel_uncore_read_fw(uncore, DSPARB);
> +		dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
>  		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
>  
>  		dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
> @@ -1800,11 +1802,11 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  		dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
>  			   VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
>  
> -		intel_uncore_write_fw(uncore, DSPARB, dsparb);
> +		intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
>  		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
>  		break;
>  	case PIPE_B:
> -		dsparb = intel_uncore_read_fw(uncore, DSPARB);
> +		dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
>  		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
>  
>  		dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
> @@ -1817,7 +1819,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  		dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
>  			   VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
>  
> -		intel_uncore_write_fw(uncore, DSPARB, dsparb);
> +		intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
>  		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
>  		break;
>  	case PIPE_C:
> @@ -1841,7 +1843,7 @@ static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
>  		break;
>  	}
>  
> -	intel_uncore_posting_read_fw(uncore, DSPARB);
> +	intel_uncore_posting_read_fw(uncore, DSPARB(dev_priv));
>  
>  	spin_unlock(&uncore->lock);
>  }
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index cbe109973f57..75223b8cb575 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -1984,7 +1984,7 @@
>  #define   SPRITEA_INVALID_GTT_STATUS			REG_BIT(1)
>  #define   PLANEA_INVALID_GTT_STATUS			REG_BIT(0)
>  
> -#define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
> +#define DSPARB(dev_priv)			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
>  #define   DSPARB_CSTART_MASK	(0x7f << 7)
>  #define   DSPARB_CSTART_SHIFT	7
>  #define   DSPARB_BSTART_MASK	(0x7f)
> diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
> index 81def10eb58f..bc449613c848 100644
> --- a/drivers/gpu/drm/i915/i915_suspend.c
> +++ b/drivers/gpu/drm/i915/i915_suspend.c
> @@ -92,7 +92,8 @@ void i915_save_display(struct drm_i915_private *dev_priv)
>  
>  	/* Display arbitration control */
>  	if (GRAPHICS_VER(dev_priv) <= 4)
> -		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);
> +		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv,
> +							     DSPARB(dev_priv));
>  
>  	if (GRAPHICS_VER(dev_priv) == 4)
>  		pci_read_config_word(pdev, GCDGMBUS,
> @@ -116,7 +117,8 @@ void i915_restore_display(struct drm_i915_private *dev_priv)
>  
>  	/* Display arbitration */
>  	if (GRAPHICS_VER(dev_priv) <= 4)
> -		intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB);
> +		intel_de_write(dev_priv, DSPARB(dev_priv),
> +			       dev_priv->regfile.saveDSPARB);
>  
>  	intel_vga_redisable(dev_priv);
>  
> -- 
> 2.39.2
>
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/i9xx_wm.c b/drivers/gpu/drm/i915/display/i9xx_wm.c
index 628e7192ebc9..fd14010b4cc3 100644
--- a/drivers/gpu/drm/i915/display/i9xx_wm.c
+++ b/drivers/gpu/drm/i915/display/i9xx_wm.c
@@ -269,13 +269,15 @@  static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 
 	switch (pipe) {
 	case PIPE_A:
-		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+		dsparb = intel_uncore_read(&dev_priv->uncore,
+					   DSPARB(dev_priv));
 		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
 		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
 		break;
 	case PIPE_B:
-		dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+		dsparb = intel_uncore_read(&dev_priv->uncore,
+					   DSPARB(dev_priv));
 		dsparb2 = intel_uncore_read(&dev_priv->uncore, DSPARB2);
 		sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
 		sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
@@ -300,7 +302,7 @@  static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state)
 static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
 			      enum i9xx_plane_id i9xx_plane)
 {
-	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
 	int size;
 
 	size = dsparb & 0x7f;
@@ -316,7 +318,7 @@  static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv,
 static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
 			      enum i9xx_plane_id i9xx_plane)
 {
-	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
 	int size;
 
 	size = dsparb & 0x1ff;
@@ -333,7 +335,7 @@  static int i830_get_fifo_size(struct drm_i915_private *dev_priv,
 static int i845_get_fifo_size(struct drm_i915_private *dev_priv,
 			      enum i9xx_plane_id i9xx_plane)
 {
-	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB);
+	u32 dsparb = intel_uncore_read(&dev_priv->uncore, DSPARB(dev_priv));
 	int size;
 
 	size = dsparb & 0x7f;
@@ -1787,7 +1789,7 @@  static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 
 	switch (crtc->pipe) {
 	case PIPE_A:
-		dsparb = intel_uncore_read_fw(uncore, DSPARB);
+		dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
 		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
 
 		dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
@@ -1800,11 +1802,11 @@  static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 		dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
 			   VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
 
-		intel_uncore_write_fw(uncore, DSPARB, dsparb);
+		intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
 		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
 		break;
 	case PIPE_B:
-		dsparb = intel_uncore_read_fw(uncore, DSPARB);
+		dsparb = intel_uncore_read_fw(uncore, DSPARB(dev_priv));
 		dsparb2 = intel_uncore_read_fw(uncore, DSPARB2);
 
 		dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
@@ -1817,7 +1819,7 @@  static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 		dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
 			   VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
 
-		intel_uncore_write_fw(uncore, DSPARB, dsparb);
+		intel_uncore_write_fw(uncore, DSPARB(dev_priv), dsparb);
 		intel_uncore_write_fw(uncore, DSPARB2, dsparb2);
 		break;
 	case PIPE_C:
@@ -1841,7 +1843,7 @@  static void vlv_atomic_update_fifo(struct intel_atomic_state *state,
 		break;
 	}
 
-	intel_uncore_posting_read_fw(uncore, DSPARB);
+	intel_uncore_posting_read_fw(uncore, DSPARB(dev_priv));
 
 	spin_unlock(&uncore->lock);
 }
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index cbe109973f57..75223b8cb575 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -1984,7 +1984,7 @@ 
 #define   SPRITEA_INVALID_GTT_STATUS			REG_BIT(1)
 #define   PLANEA_INVALID_GTT_STATUS			REG_BIT(0)
 
-#define DSPARB			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
+#define DSPARB(dev_priv)			_MMIO(DISPLAY_MMIO_BASE(dev_priv) + 0x70030)
 #define   DSPARB_CSTART_MASK	(0x7f << 7)
 #define   DSPARB_CSTART_SHIFT	7
 #define   DSPARB_BSTART_MASK	(0x7f)
diff --git a/drivers/gpu/drm/i915/i915_suspend.c b/drivers/gpu/drm/i915/i915_suspend.c
index 81def10eb58f..bc449613c848 100644
--- a/drivers/gpu/drm/i915/i915_suspend.c
+++ b/drivers/gpu/drm/i915/i915_suspend.c
@@ -92,7 +92,8 @@  void i915_save_display(struct drm_i915_private *dev_priv)
 
 	/* Display arbitration control */
 	if (GRAPHICS_VER(dev_priv) <= 4)
-		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv, DSPARB);
+		dev_priv->regfile.saveDSPARB = intel_de_read(dev_priv,
+							     DSPARB(dev_priv));
 
 	if (GRAPHICS_VER(dev_priv) == 4)
 		pci_read_config_word(pdev, GCDGMBUS,
@@ -116,7 +117,8 @@  void i915_restore_display(struct drm_i915_private *dev_priv)
 
 	/* Display arbitration */
 	if (GRAPHICS_VER(dev_priv) <= 4)
-		intel_de_write(dev_priv, DSPARB, dev_priv->regfile.saveDSPARB);
+		intel_de_write(dev_priv, DSPARB(dev_priv),
+			       dev_priv->regfile.saveDSPARB);
 
 	intel_vga_redisable(dev_priv);