| Message ID | 20240606182800.415831-1-jesse@rivosinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 04a2aef59cfe192aa99020601d922359978cc72a |
| Headers | show |
| Series | RISC-V: fix vector insn load/store width mask | expand |
On Thu, Jun 06, 2024 at 02:28:00PM -0400, Jesse Taube wrote: > RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits. > Replace GENMASK(3, 0) with GENMASK(2, 0). > > Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap") > Signed-off-by: Jesse Taube <jesse@rivosinc.com> > --- > arch/riscv/include/asm/insn.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h > index 06e439eeef9a..09fde95a5e8f 100644 > --- a/arch/riscv/include/asm/insn.h > +++ b/arch/riscv/include/asm/insn.h > @@ -145,7 +145,7 @@ > > /* parts of opcode for RVF, RVD and RVQ */ > #define RVFDQ_FL_FS_WIDTH_OFF 12 > -#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(3, 0) > +#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(2, 0) > #define RVFDQ_FL_FS_WIDTH_W 2 > #define RVFDQ_FL_FS_WIDTH_D 3 > #define RVFDQ_LS_FS_WIDTH_Q 4 > -- > 2.43.0 > Thanks! Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
Hello: This patch was applied to riscv/linux.git (fixes) by Palmer Dabbelt <palmer@rivosinc.com>: On Thu, 6 Jun 2024 14:28:00 -0400 you wrote: > RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits. > Replace GENMASK(3, 0) with GENMASK(2, 0). > > Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap") > Signed-off-by: Jesse Taube <jesse@rivosinc.com> > --- > arch/riscv/include/asm/insn.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Here is the summary with links: - RISC-V: fix vector insn load/store width mask https://git.kernel.org/riscv/c/04a2aef59cfe You are awesome, thank you!
diff --git a/arch/riscv/include/asm/insn.h b/arch/riscv/include/asm/insn.h index 06e439eeef9a..09fde95a5e8f 100644 --- a/arch/riscv/include/asm/insn.h +++ b/arch/riscv/include/asm/insn.h @@ -145,7 +145,7 @@ /* parts of opcode for RVF, RVD and RVQ */ #define RVFDQ_FL_FS_WIDTH_OFF 12 -#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(3, 0) +#define RVFDQ_FL_FS_WIDTH_MASK GENMASK(2, 0) #define RVFDQ_FL_FS_WIDTH_W 2 #define RVFDQ_FL_FS_WIDTH_D 3 #define RVFDQ_LS_FS_WIDTH_Q 4
RVFDQ_FL_FS_WIDTH_MASK should be 3 bits [14-12], shifted down by 12 bits. Replace GENMASK(3, 0) with GENMASK(2, 0). Fixes: cd054837243b ("riscv: Allocate user's vector context in the first-use trap") Signed-off-by: Jesse Taube <jesse@rivosinc.com> --- arch/riscv/include/asm/insn.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)