diff mbox series

[v2,1/9] arm64: dts: imx8: add basic lvds and lvds2 subsystem

Message ID 20240610-imx8qm-dts-usb-v2-1-788417116fb1@nxp.com (mailing list archive)
State Superseded
Headers show
Series arm64: dts: imx8qm: add subsystem lvds and mipi | expand

Commit Message

Frank Li June 10, 2024, 8:46 p.m. UTC 
Add basic lvds and lvds2 subsystem for imx8qm an imx8qxp.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi |  63 +++++++++++++
 arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi | 114 +++++++++++++++++++++++
 2 files changed, 177 insertions(+)

Comments

Alexander Stein June 11, 2024, 10:05 a.m. UTC | #1 
Hi Frank,

Am Montag, 10. Juni 2024, 22:46:18 CEST schrieb Frank Li:
> Add basic lvds and lvds2 subsystem for imx8qm an imx8qxp.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi |  63 +++++++++++++
>  arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi | 114 +++++++++++++++++++++++
>  2 files changed, 177 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
> new file mode 100644
> index 0000000000000..55fd60446ad21
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
> @@ -0,0 +1,63 @@
> +// SPDX-License-Identifier: GPL-2.0-only and MIT
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +lvds0_subsys: bus@56240000 {
> +	compatible = "simple-bus";
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	ranges = <0x56240000 0x0 0x56240000 0x10000>;
> +
> +	qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x56243000 0x4>;
> +		#clock-cells = <1>;
> +		clock-output-names = "mipi1_lis_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1>;
> +	};
> +
> +	qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5624300c 0x4>;
> +		#clock-cells = <1>;
> +		clock-output-names = "mipi1_pwm_lpcg_clk",
> +				     "mipi1_pwm_lpcg_ipg_clk",
> +				     "mipi1_pwm_lpcg_32k_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> +	};
> +
> +	qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x56243010 0x4>;
> +		#clock-cells = <1>;
> +		clock-output-names = "mipi1_i2c0_lpcg_clk",
> +				     "mipi1_i2c0_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> +	};
> +
> +	qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 {
> +		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> +		reg = <0x56244000 0x1000>;
> +		clock-names = "ipg", "per";
> +		assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;

Is IMX_SC_R_MIPI_1_I2C_0 actually correct? I would have assumed
it's IMX_SC_R_MIPI_1_PWM_0.

> +		assigned-clock-rates = <24000000>;
> +		#pwm-cells = <3>;
> +		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> +		status = "disabled";
> +	};
> +
> +	qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 {
> +		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg = <0x56246000 0x1000>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		interrupts = <8>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <24000000>;
> +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> +		status = "disabled";
> +	};
> +};
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
> new file mode 100644
> index 0000000000000..12ae4f48e1e1c
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi

This is only for imx8qm, no?

It maybe makes sense to rename this file to imx8qm-ss-lvds1.dtsi

Best regards,
Alexander

> @@ -0,0 +1,114 @@
> +// SPDX-License-Identifier: GPL-2.0-only and MIT
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +lvds1_subsys: bus@57240000 {
> +	compatible = "simple-bus";
> +	interrupt-parent = <&irqsteer_lvds1>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	ranges = <0x57240000 0x0 0x57240000 0x10000>;
> +
> +	irqsteer_lvds1: interrupt-controller@57240000 {
> +		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> +		reg = <0x57240000 0x1000>;
> +		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-controller;
> +		interrupt-parent = <&gic>;
> +		#interrupt-cells = <1>;
> +		clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
> +		clock-names = "ipg";
> +		power-domains = <&pd IMX_SC_R_LVDS_1>;
> +		fsl,channel = <0>;
> +		fsl,num-irqs = <32>;
> +	};
> +
> +	lvds1_lis_lpcg: clock-controller@57243000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x57243000 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&lvds_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_4>;
> +		clock-output-names = "lvds1_lis_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_LVDS_1>;
> +	};
> +
> +	lvds1_pwm_lpcg: clock-controller@5724300c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5724300c 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
> +			 <&lvds_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> +		clock-output-names = "lvds1_pwm_lpcg_clk",
> +				     "lvds1_pwm_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
> +	};
> +
> +	lvds1_i2c0_lpcg: clock-controller@57243010 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x57243010 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
> +			 <&lvds_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> +		clock-output-names = "lvds1_i2c0_lpcg_clk",
> +				     "lvds1_i2c0_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> +	};
> +
> +	lvds1_i2c1_lpcg: clock-controller@57243014 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x57243014 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
> +			 <&lvds_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> +		clock-output-names = "lvds1_i2c1_lpcg_clk",
> +				     "lvds1_i2c1_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> +	};
> +
> +	pwm_lvds1: pwm@57244000 {
> +		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> +		reg = <0x57244000 0x1000>;
> +		clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
> +			 <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
> +		clock-names = "ipg", "per";
> +		assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <24000000>;
> +		#pwm-cells = <3>;
> +		power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
> +		status = "disabled";
> +	};
> +
> +	i2c0_lvds1: i2c@57246000 {
> +		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg = <0x57246000 0x1000>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		interrupts = <8>;
> +		clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
> +			 <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <24000000>;
> +		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> +		status = "disabled";
> +	};
> +
> +	i2c1_lvds1: i2c@57247000 {
> +		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg = <0x57247000 0x1000>;
> +		interrupts = <9>;
> +		clocks = <&lvds1_i2c1_lpcg IMX_LPCG_CLK_0>,
> +			 <&lvds1_i2c1_lpcg IMX_LPCG_CLK_4>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <24000000>;
> +		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> +		status = "disabled";
> +	};
> +};
> 
>
Frank Li June 12, 2024, 3:13 p.m. UTC | #2 
On Tue, Jun 11, 2024 at 12:05:35PM +0200, Alexander Stein wrote:
> Hi Frank,
> 
> Am Montag, 10. Juni 2024, 22:46:18 CEST schrieb Frank Li:
> > Add basic lvds and lvds2 subsystem for imx8qm an imx8qxp.
> > 
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi |  63 +++++++++++++
> >  arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi | 114 +++++++++++++++++++++++
> >  2 files changed, 177 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
> > new file mode 100644
> > index 0000000000000..55fd60446ad21
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
> > @@ -0,0 +1,63 @@
> > +// SPDX-License-Identifier: GPL-2.0-only and MIT
> > +
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +lvds0_subsys: bus@56240000 {
> > +	compatible = "simple-bus";
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +	ranges = <0x56240000 0x0 0x56240000 0x10000>;
> > +
> > +	qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x56243000 0x4>;
> > +		#clock-cells = <1>;
> > +		clock-output-names = "mipi1_lis_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1>;
> > +	};
> > +
> > +	qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x5624300c 0x4>;
> > +		#clock-cells = <1>;
> > +		clock-output-names = "mipi1_pwm_lpcg_clk",
> > +				     "mipi1_pwm_lpcg_ipg_clk",
> > +				     "mipi1_pwm_lpcg_32k_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> > +	};
> > +
> > +	qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x56243010 0x4>;
> > +		#clock-cells = <1>;
> > +		clock-output-names = "mipi1_i2c0_lpcg_clk",
> > +				     "mipi1_i2c0_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > +	};
> > +
> > +	qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 {
> > +		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> > +		reg = <0x56244000 0x1000>;
> > +		clock-names = "ipg", "per";
> > +		assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
> 
> Is IMX_SC_R_MIPI_1_I2C_0 actually correct? I would have assumed
> it's IMX_SC_R_MIPI_1_PWM_0.
> 
> > +		assigned-clock-rates = <24000000>;
> > +		#pwm-cells = <3>;
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 {
> > +		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
> > +		reg = <0x56246000 0x1000>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		interrupts = <8>;
> > +		clock-names = "per", "ipg";
> > +		assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
> > +		assigned-clock-rates = <24000000>;
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > +		status = "disabled";
> > +	};
> > +};
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
> > new file mode 100644
> > index 0000000000000..12ae4f48e1e1c
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
> 
> This is only for imx8qm, no?
> 
> It maybe makes sense to rename this file to imx8qm-ss-lvds1.dtsi

It plan include in root node, it'd better keep consistency with other
file names.

        /* sorted in register address */                                                            
        #include "imx8-ss-audio.dtsi"                                                               
        #include "imx8-ss-img.dtsi"                                                                 
        #include "imx8-ss-dma.dtsi"                                                                 
        #include "imx8-ss-security.dtsi"                                                            
        #include "imx8-ss-cm41.dtsi"                                                                
        #include "imx8-ss-conn.dtsi"                                                                
        #include "imx8-ss-ddr.dtsi"                                                                 
        #include "imx8-ss-lsio.dtsi"                                                                
        #include "imx8-ss-hsio.dtsi"                                                                
        #include "imx8-ss-dc0.dtsi"                                                                 
        #include "imx8-ss-dc1.dtsi"                                                                 
        #include "imx8-ss-gpu0.dtsi"                                                                
        #include "imx8-ss-gpu1.dtsi"                                                                
        #include "imx8-ss-vpu.dtsi"  

}

imx8qm-ss-xxx should overwrite common ss part.

Frank

> 
> Best regards,
> Alexander
> 
> > @@ -0,0 +1,114 @@
> > +// SPDX-License-Identifier: GPL-2.0-only and MIT
> > +
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +lvds1_subsys: bus@57240000 {
> > +	compatible = "simple-bus";
> > +	interrupt-parent = <&irqsteer_lvds1>;
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +	ranges = <0x57240000 0x0 0x57240000 0x10000>;
> > +
> > +	irqsteer_lvds1: interrupt-controller@57240000 {
> > +		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> > +		reg = <0x57240000 0x1000>;
> > +		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
> > +		interrupt-controller;
> > +		interrupt-parent = <&gic>;
> > +		#interrupt-cells = <1>;
> > +		clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
> > +		clock-names = "ipg";
> > +		power-domains = <&pd IMX_SC_R_LVDS_1>;
> > +		fsl,channel = <0>;
> > +		fsl,num-irqs = <32>;
> > +	};
> > +
> > +	lvds1_lis_lpcg: clock-controller@57243000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x57243000 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&lvds_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "lvds1_lis_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_LVDS_1>;
> > +	};
> > +
> > +	lvds1_pwm_lpcg: clock-controller@5724300c {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x5724300c 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
> > +			 <&lvds_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "lvds1_pwm_lpcg_clk",
> > +				     "lvds1_pwm_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
> > +	};
> > +
> > +	lvds1_i2c0_lpcg: clock-controller@57243010 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x57243010 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
> > +			 <&lvds_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "lvds1_i2c0_lpcg_clk",
> > +				     "lvds1_i2c0_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> > +	};
> > +
> > +	lvds1_i2c1_lpcg: clock-controller@57243014 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x57243014 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
> > +			 <&lvds_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "lvds1_i2c1_lpcg_clk",
> > +				     "lvds1_i2c1_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> > +	};
> > +
> > +	pwm_lvds1: pwm@57244000 {
> > +		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> > +		reg = <0x57244000 0x1000>;
> > +		clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
> > +			 <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
> > +		clock-names = "ipg", "per";
> > +		assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
> > +		assigned-clock-rates = <24000000>;
> > +		#pwm-cells = <3>;
> > +		power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	i2c0_lvds1: i2c@57246000 {
> > +		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> > +		reg = <0x57246000 0x1000>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		interrupts = <8>;
> > +		clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
> > +			 <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
> > +		clock-names = "per", "ipg";
> > +		assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
> > +		assigned-clock-rates = <24000000>;
> > +		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	i2c1_lvds1: i2c@57247000 {
> > +		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> > +		reg = <0x57247000 0x1000>;
> > +		interrupts = <9>;
> > +		clocks = <&lvds1_i2c1_lpcg IMX_LPCG_CLK_0>,
> > +			 <&lvds1_i2c1_lpcg IMX_LPCG_CLK_4>;
> > +		clock-names = "per", "ipg";
> > +		assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
> > +		assigned-clock-rates = <24000000>;
> > +		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
> > +		status = "disabled";
> > +	};
> > +};
> > 
> > 
> 
> 
> -- 
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-group.com/
> 
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
new file mode 100644
index 0000000000000..55fd60446ad21
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds0.dtsi
@@ -0,0 +1,63 @@ 
+// SPDX-License-Identifier: GPL-2.0-only and MIT
+
+/*
+ * Copyright 2024 NXP
+ */
+
+lvds0_subsys: bus@56240000 {
+	compatible = "simple-bus";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x56240000 0x0 0x56240000 0x10000>;
+
+	qm_lvds0_lis_lpcg: qxp_mipi1_lis_lpcg: clock-controller@56243000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x56243000 0x4>;
+		#clock-cells = <1>;
+		clock-output-names = "mipi1_lis_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1>;
+	};
+
+	qm_lvds0_pwm_lpcg: qxp_mipi1_pwm_lpcg: clock-controller@5624300c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5624300c 0x4>;
+		#clock-cells = <1>;
+		clock-output-names = "mipi1_pwm_lpcg_clk",
+				     "mipi1_pwm_lpcg_ipg_clk",
+				     "mipi1_pwm_lpcg_32k_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+	};
+
+	qm_lvds0_i2c0_lpcg: qxp_mipi1_i2c0_lpcg: clock-controller@56243010 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x56243010 0x4>;
+		#clock-cells = <1>;
+		clock-output-names = "mipi1_i2c0_lpcg_clk",
+				     "mipi1_i2c0_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+	};
+
+	qm_pwm_lvds0: qxp_pwm_mipi_lvds1: pwm@56244000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x56244000 0x1000>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <3>;
+		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+		status = "disabled";
+	};
+
+	qm_i2c0_lvds0: qxp_i2c0_mipi_lvds1: i2c@56246000 {
+		compatible = "fsl,imx8qxp-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x56246000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <8>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+		status = "disabled";
+	};
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
new file mode 100644
index 0000000000000..12ae4f48e1e1c
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-lvds1.dtsi
@@ -0,0 +1,114 @@ 
+// SPDX-License-Identifier: GPL-2.0-only and MIT
+
+/*
+ * Copyright 2024 NXP
+ */
+
+lvds1_subsys: bus@57240000 {
+	compatible = "simple-bus";
+	interrupt-parent = <&irqsteer_lvds1>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x57240000 0x0 0x57240000 0x10000>;
+
+	irqsteer_lvds1: interrupt-controller@57240000 {
+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
+		reg = <0x57240000 0x1000>;
+		interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <1>;
+		clocks = <&lvds1_lis_lpcg IMX_LPCG_CLK_4>;
+		clock-names = "ipg";
+		power-domains = <&pd IMX_SC_R_LVDS_1>;
+		fsl,channel = <0>;
+		fsl,num-irqs = <32>;
+	};
+
+	lvds1_lis_lpcg: clock-controller@57243000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57243000 0x4>;
+		#clock-cells = <1>;
+		clocks = <&lvds_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_4>;
+		clock-output-names = "lvds1_lis_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_LVDS_1>;
+	};
+
+	lvds1_pwm_lpcg: clock-controller@5724300c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5724300c 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
+			 <&lvds_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "lvds1_pwm_lpcg_clk",
+				     "lvds1_pwm_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+	};
+
+	lvds1_i2c0_lpcg: clock-controller@57243010 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57243010 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+			 <&lvds_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "lvds1_i2c0_lpcg_clk",
+				     "lvds1_i2c0_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+	};
+
+	lvds1_i2c1_lpcg: clock-controller@57243014 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57243014 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>,
+			 <&lvds_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "lvds1_i2c1_lpcg_clk",
+				     "lvds1_i2c1_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+	};
+
+	pwm_lvds1: pwm@57244000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x57244000 0x1000>;
+		clocks = <&lvds1_pwm_lpcg IMX_LPCG_CLK_4>,
+			 <&lvds1_pwm_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <3>;
+		power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+		status = "disabled";
+	};
+
+	i2c0_lvds1: i2c@57246000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x57246000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <8>;
+		clocks = <&lvds1_i2c0_lpcg IMX_LPCG_CLK_0>,
+			 <&lvds1_i2c0_lpcg IMX_LPCG_CLK_4>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+		status = "disabled";
+	};
+
+	i2c1_lvds1: i2c@57247000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x57247000 0x1000>;
+		interrupts = <9>;
+		clocks = <&lvds1_i2c1_lpcg IMX_LPCG_CLK_0>,
+			 <&lvds1_i2c1_lpcg IMX_LPCG_CLK_4>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&clk IMX_SC_R_LVDS_1_I2C_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_LVDS_1_I2C_0>;
+		status = "disabled";
+	};
+};