diff mbox series

[v2,3/9] arm64: dts: imx8: add basic mipi subsystem

Message ID 20240610-imx8qm-dts-usb-v2-3-788417116fb1@nxp.com (mailing list archive)
State Superseded
Headers show
Series arm64: dts: imx8qm: add subsystem lvds and mipi | expand

Commit Message

Frank Li June 10, 2024, 8:46 p.m. UTC 
Add basic mipi subsystem for imx8qm and imx8qxp.

Signed-off-by: Frank Li <Frank.Li@nxp.com>
---
 arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi | 138 +++++++++++++++++++++++
 arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi | 138 +++++++++++++++++++++++
 2 files changed, 276 insertions(+)

Comments

Alexander Stein June 11, 2024, 11:14 a.m. UTC | #1 
Am Montag, 10. Juni 2024, 22:46:20 CEST schrieb Frank Li:
> ********************
> Achtung externe E-Mail: Öffnen Sie Anhänge und Links nur, wenn Sie wissen, dass diese aus einer sicheren Quelle stammen und sicher sind. Leiten Sie die E-Mail im Zweifelsfall zur Prüfung an den IT-Helpdesk weiter.
> Attention external email: Open attachments and links only if you know that they are from a secure source and are safe. In doubt forward the email to the IT-Helpdesk to check it.
> ********************
> 
> Add basic mipi subsystem for imx8qm and imx8qxp.
> 
> Signed-off-by: Frank Li <Frank.Li@nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi | 138 +++++++++++++++++++++++
>  arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi | 138 +++++++++++++++++++++++
>  2 files changed, 276 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
> new file mode 100644
> index 0000000000000..6b56315e8c434
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0-only and MIT
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +mipi0_subsys: bus@56220000 {
> +	compatible = "simple-bus";
> +	interrupt-parent = <&irqsteer_mipi0>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	ranges = <0x56220000 0x0 0x56220000 0x10000>;
> +
> +	irqsteer_mipi0: interrupt-controller@56220000 {
> +		compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
> +		reg = <0x56220000 0x1000>;
> +		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-controller;
> +		interrupt-parent = <&gic>;
> +		#interrupt-cells = <1>;
> +		clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
> +		clock-names = "ipg";
> +		power-domains = <&pd IMX_SC_R_MIPI_0>;
> +		fsl,channel = <0>;
> +		fsl,num-irqs = <32>;
> +	};
> +
> +	mipi0_lis_lpcg: clock-controller@56223000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x56223000 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&dsi_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>;

That's LPCG_DI_LVDS_LPCG_0 for imx8qxp, no? So clock-indices and
clock-output-names should be split similar to patch.

> +		clock-output-names = "mipi0_lis_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_0>;
> +	};
> +
> +	mipi0_pwm_lpcg: clock-controller@5622300c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5622300c 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
> +			 <&dsi_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> +		clock-output-names = "mipi0_pwm_lpcg_clk",
> +				     "mipi0_pwm_lpcg_ipg_clk";

That's LPCG_DI_MIPI_LPCG_12, no? imx8qm RM Rev 0 just lists one clock.
Also it's different on imx8qxp.

> +		power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> +	};
> +
> +	mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x56223014 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;

Just 0 instead of IMX_LPCG_CLK_0.

> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> +	};
> +
> +	mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x56223018 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&dsi_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> +	};
> +
> +	mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5622301c 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi0_i2c0_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> +	};
> +
> +	mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x56223024 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> +	};
> +
> +	mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5622302c 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi0_i2c1_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> +	};
> +
> +	mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x56223028 0x4>;

Order nodes by base address please.

> +		#clock-cells = <1>;
> +		clocks = <&dsi_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> +	};
> +
> +	pwm_mipi0: pwm@56224000 {
> +		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> +		reg = <0x56224000 0x1000>;
> +		clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
> +			 <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;

I don't think that's correct. IMX_LPCG_CLK_4 evaluates to 16.
'mipi0_pwm_lpcg' only has 2 clocks, so you should use just '1' and '0'.

> +		clock-names = "ipg", "per";
> +		assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <24000000>;
> +		#pwm-cells = <3>;
> +		power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> +		status = "disabled";
> +	};
> +
> +	i2c0_mipi0: i2c@56226000 {
> +		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg = <0x56226000 0x1000>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		interrupts = <8>;
> +		clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> +			 <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;

Just use 0 instead of IMX_LPCG_CLK_0.

> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> +		assigned-clock-rates = <24000000>;
> +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> +		status = "disabled";
> +	};
> +};
> +
> diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
> new file mode 100644
> index 0000000000000..5b1f08e412b24
> --- /dev/null
> +++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi

This is only for imx8qm, no?

It maybe makes sense to rename this file to imx8qm-ss-mipi1.dtsi

Best regards,
Alexander

> @@ -0,0 +1,138 @@
> +// SPDX-License-Identifier: GPL-2.0-only and MIT
> +
> +/*
> + * Copyright 2024 NXP
> + */
> +
> +mipi1_subsys: bus@57220000 {
> +	compatible = "simple-bus";
> +	interrupt-parent = <&irqsteer_mipi1>;
> +	#address-cells = <1>;
> +	#size-cells = <1>;
> +	ranges = <0x57220000 0x0 0x57220000 0x10000>;
> +
> +	irqsteer_mipi1: interrupt-controller@57220000 {
> +		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> +		reg = <0x57220000 0x1000>;
> +		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> +		interrupt-controller;
> +		interrupt-parent = <&gic>;
> +		#interrupt-cells = <1>;
> +		clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
> +		clock-names = "ipg";
> +		power-domains = <&pd IMX_SC_R_MIPI_1>;
> +		fsl,channel = <0>;
> +		fsl,num-irqs = <32>;
> +	};
> +
> +	mipi1_lis_lpcg: clock-controller@57223000 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x57223000 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&dsi_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi1_lis_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1>;
> +	};
> +
> +	mipi1_pwm_lpcg: clock-controller@5722300c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5722300c 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
> +			 <&dsi_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> +		clock-output-names = "mipi1_pwm_lpcg_clk",
> +				     "mipi1_pwm_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> +	};
> +
> +	mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5722301c 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi1_i2c0_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> +	};
> +
> +	mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x57223014 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> +	};
> +
> +	mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x57223018 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&dsi_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> +	};
> +
> +	mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x57223024 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> +	};
> +
> +	mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x57223028 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&dsi_ipg_clk>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> +	};
> +
> +	mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
> +		compatible = "fsl,imx8qxp-lpcg";
> +		reg = <0x5722302c 0x4>;
> +		#clock-cells = <1>;
> +		clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
> +		clock-indices = <IMX_LPCG_CLK_0>;
> +		clock-output-names = "mipi1_i2c1_lpcg_clk";
> +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> +	};
> +
> +	pwm_mipi1: pwm@57224000 {
> +		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> +		reg = <0x57224000 0x1000>;
> +		clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
> +			 <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
> +		clock-names = "ipg", "per";
> +		assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
> +		assigned-clock-rates = <24000000>;
> +		#pwm-cells = <3>;
> +		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> +		status = "disabled";
> +	};
> +
> +	i2c0_mipi1: i2c@57226000 {
> +		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> +		reg = <0x57226000 0x1000>;
> +		#address-cells = <1>;
> +		#size-cells = <0>;
> +		interrupts = <8>;
> +		interrupt-parent = <&irqsteer_mipi1>;
> +		clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> +			 <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
> +		clock-names = "per", "ipg";
> +		assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> +		assigned-clock-rates = <24000000>;
> +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> +		status = "disabled";
> +	};
> +};
> 
>
Frank Li June 11, 2024, 3:03 p.m. UTC | #2 
On Tue, Jun 11, 2024 at 01:14:20PM +0200, Alexander Stein wrote:
> Am Montag, 10. Juni 2024, 22:46:20 CEST schrieb Frank Li:
> > ********************
> > Achtung externe E-Mail: Öffnen Sie Anhänge und Links nur, wenn Sie wissen, dass diese aus einer sicheren Quelle stammen und sicher sind. Leiten Sie die E-Mail im Zweifelsfall zur Prüfung an den IT-Helpdesk weiter.
> > Attention external email: Open attachments and links only if you know that they are from a secure source and are safe. In doubt forward the email to the IT-Helpdesk to check it.
> > ********************
> > 
> > Add basic mipi subsystem for imx8qm and imx8qxp.
> > 
> > Signed-off-by: Frank Li <Frank.Li@nxp.com>
> > ---
> >  arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi | 138 +++++++++++++++++++++++
> >  arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi | 138 +++++++++++++++++++++++
> >  2 files changed, 276 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
> > new file mode 100644
> > index 0000000000000..6b56315e8c434
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
> > @@ -0,0 +1,138 @@
> > +// SPDX-License-Identifier: GPL-2.0-only and MIT
> > +
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +mipi0_subsys: bus@56220000 {
> > +	compatible = "simple-bus";
> > +	interrupt-parent = <&irqsteer_mipi0>;
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +	ranges = <0x56220000 0x0 0x56220000 0x10000>;
> > +
> > +	irqsteer_mipi0: interrupt-controller@56220000 {
> > +		compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
> > +		reg = <0x56220000 0x1000>;
> > +		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
> > +		interrupt-controller;
> > +		interrupt-parent = <&gic>;
> > +		#interrupt-cells = <1>;
> > +		clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
> > +		clock-names = "ipg";
> > +		power-domains = <&pd IMX_SC_R_MIPI_0>;
> > +		fsl,channel = <0>;
> > +		fsl,num-irqs = <32>;
> > +	};
> > +
> > +	mipi0_lis_lpcg: clock-controller@56223000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x56223000 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&dsi_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> 
> That's LPCG_DI_LVDS_LPCG_0 for imx8qxp, no? So clock-indices and
> clock-output-names should be split similar to patch.

I am focus qm firstly. I can remove it. 

> 
> > +		clock-output-names = "mipi0_lis_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_0>;
> > +	};
> > +
> > +	mipi0_pwm_lpcg: clock-controller@5622300c {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x5622300c 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
> > +			 <&dsi_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "mipi0_pwm_lpcg_clk",
> > +				     "mipi0_pwm_lpcg_ipg_clk";
> 
> That's LPCG_DI_MIPI_LPCG_12, no? imx8qm RM Rev 0 just lists one clock.
> Also it's different on imx8qxp.
> 
> > +		power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> > +	};
> > +
> > +	mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x56223014 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> 
> Just 0 instead of IMX_LPCG_CLK_0.

all lpcg have to use IMX_LPCG_CLK_n, down stream clk driver is difference
with upstream one.

> 
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> > +	};
> > +
> > +	mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x56223018 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&dsi_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> > +	};
> > +
> > +	mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x5622301c 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi0_i2c0_lpcg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> > +	};
> > +
> > +	mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x56223024 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> > +	};
> > +
> > +	mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x5622302c 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi0_i2c1_lpcg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> > +	};
> > +
> > +	mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x56223028 0x4>;
> 
> Order nodes by base address please.
> 
> > +		#clock-cells = <1>;
> > +		clocks = <&dsi_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
> > +	};
> > +
> > +	pwm_mipi0: pwm@56224000 {
> > +		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> > +		reg = <0x56224000 0x1000>;
> > +		clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
> > +			 <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;
> 
> I don't think that's correct. IMX_LPCG_CLK_4 evaluates to 16.
> 'mipi0_pwm_lpcg' only has 2 clocks, so you should use just '1' and '0'.

all lpcg have to use indices, instead of index. Upstream clk driver use
arg0 as clock indices, which is difference downstream version. 

> 
> > +		clock-names = "ipg", "per";
> > +		assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
> > +		assigned-clock-rates = <24000000>;
> > +		#pwm-cells = <3>;
> > +		power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	i2c0_mipi0: i2c@56226000 {
> > +		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> > +		reg = <0x56226000 0x1000>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		interrupts = <8>;
> > +		clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> > +			 <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
> 
> Just use 0 instead of IMX_LPCG_CLK_0.
> 
> > +		clock-names = "per", "ipg";
> > +		assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> > +		assigned-clock-rates = <24000000>;
> > +		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
> > +		status = "disabled";
> > +	};
> > +};
> > +
> > diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
> > new file mode 100644
> > index 0000000000000..5b1f08e412b24
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
> 
> This is only for imx8qm, no?
> 
> It maybe makes sense to rename this file to imx8qm-ss-mipi1.dtsi
> 
> Best regards,
> Alexander
> 
> > @@ -0,0 +1,138 @@
> > +// SPDX-License-Identifier: GPL-2.0-only and MIT
> > +
> > +/*
> > + * Copyright 2024 NXP
> > + */
> > +
> > +mipi1_subsys: bus@57220000 {
> > +	compatible = "simple-bus";
> > +	interrupt-parent = <&irqsteer_mipi1>;
> > +	#address-cells = <1>;
> > +	#size-cells = <1>;
> > +	ranges = <0x57220000 0x0 0x57220000 0x10000>;
> > +
> > +	irqsteer_mipi1: interrupt-controller@57220000 {
> > +		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
> > +		reg = <0x57220000 0x1000>;
> > +		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
> > +		interrupt-controller;
> > +		interrupt-parent = <&gic>;
> > +		#interrupt-cells = <1>;
> > +		clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
> > +		clock-names = "ipg";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1>;
> > +		fsl,channel = <0>;
> > +		fsl,num-irqs = <32>;
> > +	};
> > +
> > +	mipi1_lis_lpcg: clock-controller@57223000 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x57223000 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&dsi_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi1_lis_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1>;
> > +	};
> > +
> > +	mipi1_pwm_lpcg: clock-controller@5722300c {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x5722300c 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
> > +			 <&dsi_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
> > +		clock-output-names = "mipi1_pwm_lpcg_clk",
> > +				     "mipi1_pwm_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> > +	};
> > +
> > +	mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x5722301c 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi1_i2c0_lpcg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > +	};
> > +
> > +	mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x57223014 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > +	};
> > +
> > +	mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x57223018 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&dsi_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > +	};
> > +
> > +	mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x57223024 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> > +	};
> > +
> > +	mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x57223028 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&dsi_ipg_clk>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> > +	};
> > +
> > +	mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
> > +		compatible = "fsl,imx8qxp-lpcg";
> > +		reg = <0x5722302c 0x4>;
> > +		#clock-cells = <1>;
> > +		clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
> > +		clock-indices = <IMX_LPCG_CLK_0>;
> > +		clock-output-names = "mipi1_i2c1_lpcg_clk";
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
> > +	};
> > +
> > +	pwm_mipi1: pwm@57224000 {
> > +		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
> > +		reg = <0x57224000 0x1000>;
> > +		clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
> > +			 <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
> > +		clock-names = "ipg", "per";
> > +		assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
> > +		assigned-clock-rates = <24000000>;
> > +		#pwm-cells = <3>;
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
> > +		status = "disabled";
> > +	};
> > +
> > +	i2c0_mipi1: i2c@57226000 {
> > +		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
> > +		reg = <0x57226000 0x1000>;
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		interrupts = <8>;
> > +		interrupt-parent = <&irqsteer_mipi1>;
> > +		clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
> > +			 <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
> > +		clock-names = "per", "ipg";
> > +		assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
> > +		assigned-clock-rates = <24000000>;
> > +		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
> > +		status = "disabled";
> > +	};
> > +};
> > 
> > 
> 
> 
> -- 
> TQ-Systems GmbH | Mühlstraße 2, Gut Delling | 82229 Seefeld, Germany
> Amtsgericht München, HRB 105018
> Geschäftsführer: Detlef Schneider, Rüdiger Stahl, Stefan Schneider
> http://www.tq-group.com/
> 
>
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
new file mode 100644
index 0000000000000..6b56315e8c434
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi0.dtsi
@@ -0,0 +1,138 @@ 
+// SPDX-License-Identifier: GPL-2.0-only and MIT
+
+/*
+ * Copyright 2024 NXP
+ */
+
+mipi0_subsys: bus@56220000 {
+	compatible = "simple-bus";
+	interrupt-parent = <&irqsteer_mipi0>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x56220000 0x0 0x56220000 0x10000>;
+
+	irqsteer_mipi0: interrupt-controller@56220000 {
+		compatible = "fsl,imx8qxp-irqsteer", "fsl,imx-irqsteer";
+		reg = <0x56220000 0x1000>;
+		interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <1>;
+		clocks = <&mipi0_lis_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "ipg";
+		power-domains = <&pd IMX_SC_R_MIPI_0>;
+		fsl,channel = <0>;
+		fsl,num-irqs = <32>;
+	};
+
+	mipi0_lis_lpcg: clock-controller@56223000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x56223000 0x4>;
+		#clock-cells = <1>;
+		clocks = <&dsi_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi0_lis_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_0>;
+	};
+
+	mipi0_pwm_lpcg: clock-controller@5622300c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5622300c 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>,
+			 <&dsi_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "mipi0_pwm_lpcg_clk",
+				     "mipi0_pwm_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+	};
+
+	mipi0_i2c0_lpcg_ipg_clk: clock-controller@56223014 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x56223014 0x4>;
+		#clock-cells = <1>;
+		clocks = <&mipi0_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi0_i2c0_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+	};
+
+	mipi0_i2c0_lpcg_ipg_s_clk: clock-controller@56223018 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x56223018 0x4>;
+		#clock-cells = <1>;
+		clocks = <&dsi_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi0_i2c0_lpcg_ipg_s_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+	};
+
+	mipi0_i2c0_lpcg_clk: clock-controller@5622301c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5622301c 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_MIPI_0_I2C_0 IMX_SC_PM_CLK_MISC2>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi0_i2c0_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+	};
+
+	mipi0_i2c1_lpcg_ipg_clk: clock-controller@56223024 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x56223024 0x4>;
+		#clock-cells = <1>;
+		clocks = <&mipi0_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi0_i2c1_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+	};
+
+	mipi0_i2c1_lpcg_clk: clock-controller@5622302c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5622302c 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_MIPI_0_I2C_1 IMX_SC_PM_CLK_MISC2>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi0_i2c1_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+	};
+
+	mipi0_i2c1_lpcg_ipg_s_clk: clock-controller@56223028 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x56223028 0x4>;
+		#clock-cells = <1>;
+		clocks = <&dsi_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi0_i2c1_lpcg_ipg_s_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_1>;
+	};
+
+	pwm_mipi0: pwm@56224000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x56224000 0x1000>;
+		clocks = <&mipi0_pwm_lpcg IMX_LPCG_CLK_4>,
+			 <&mipi0_pwm_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_MIPI_0_PWM_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <3>;
+		power-domains = <&pd IMX_SC_R_MIPI_0_PWM_0>;
+		status = "disabled";
+	};
+
+	i2c0_mipi0: i2c@56226000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x56226000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <8>;
+		clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
+			 <&mipi0_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&mipi0_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_MIPI_0_I2C_0>;
+		status = "disabled";
+	};
+};
+
diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
new file mode 100644
index 0000000000000..5b1f08e412b24
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8-ss-mipi1.dtsi
@@ -0,0 +1,138 @@ 
+// SPDX-License-Identifier: GPL-2.0-only and MIT
+
+/*
+ * Copyright 2024 NXP
+ */
+
+mipi1_subsys: bus@57220000 {
+	compatible = "simple-bus";
+	interrupt-parent = <&irqsteer_mipi1>;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	ranges = <0x57220000 0x0 0x57220000 0x10000>;
+
+	irqsteer_mipi1: interrupt-controller@57220000 {
+		compatible = "fsl,imx8qm-irqsteer", "fsl,imx-irqsteer";
+		reg = <0x57220000 0x1000>;
+		interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-controller;
+		interrupt-parent = <&gic>;
+		#interrupt-cells = <1>;
+		clocks = <&mipi1_lis_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "ipg";
+		power-domains = <&pd IMX_SC_R_MIPI_1>;
+		fsl,channel = <0>;
+		fsl,num-irqs = <32>;
+	};
+
+	mipi1_lis_lpcg: clock-controller@57223000 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57223000 0x4>;
+		#clock-cells = <1>;
+		clocks = <&dsi_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi1_lis_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1>;
+	};
+
+	mipi1_pwm_lpcg: clock-controller@5722300c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5722300c 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>,
+			 <&dsi_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+		clock-output-names = "mipi1_pwm_lpcg_clk",
+				     "mipi1_pwm_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+	};
+
+	mipi1_i2c0_lpcg_clk: clock-controller@5722301c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5722301c 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_MIPI_1_I2C_0 IMX_SC_PM_CLK_MISC2>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi1_i2c0_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+	};
+
+	mipi1_i2c0_lpcg_ipg_clk: clock-controller@57223014 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57223014 0x4>;
+		#clock-cells = <1>;
+		clocks = <&mipi1_i2c0_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi1_i2c0_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+	};
+
+	mipi1_i2c0_lpcg_ipg_s_clk: clock-controller@57223018 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57223018 0x4>;
+		#clock-cells = <1>;
+		clocks = <&dsi_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi1_i2c0_lpcg_ipg_s_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+	};
+
+	mipi1_i2c1_lpcg_ipg_clk: clock-controller@57223024 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57223024 0x4>;
+		#clock-cells = <1>;
+		clocks = <&mipi1_i2c1_lpcg_ipg_s_clk IMX_LPCG_CLK_0>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi1_i2c1_lpcg_ipg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+	};
+
+	mipi1_i2c1_lpcg_ipg_s_clk: clock-controller@57223028 {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x57223028 0x4>;
+		#clock-cells = <1>;
+		clocks = <&dsi_ipg_clk>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi1_i2c1_lpcg_ipg_s_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+	};
+
+	mipi1_i2c1_lpcg_clk: clock-controller@5722302c {
+		compatible = "fsl,imx8qxp-lpcg";
+		reg = <0x5722302c 0x4>;
+		#clock-cells = <1>;
+		clocks = <&clk IMX_SC_R_MIPI_1_I2C_1 IMX_SC_PM_CLK_MISC2>;
+		clock-indices = <IMX_LPCG_CLK_0>;
+		clock-output-names = "mipi1_i2c1_lpcg_clk";
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_1>;
+	};
+
+	pwm_mipi1: pwm@57224000 {
+		compatible = "fsl,imx8qxp-pwm", "fsl,imx27-pwm";
+		reg = <0x57224000 0x1000>;
+		clocks = <&mipi1_pwm_lpcg IMX_LPCG_CLK_4>,
+			 <&mipi1_pwm_lpcg IMX_LPCG_CLK_0>;
+		clock-names = "ipg", "per";
+		assigned-clocks = <&clk IMX_SC_R_MIPI_1_PWM_0 IMX_SC_PM_CLK_PER>;
+		assigned-clock-rates = <24000000>;
+		#pwm-cells = <3>;
+		power-domains = <&pd IMX_SC_R_MIPI_1_PWM_0>;
+		status = "disabled";
+	};
+
+	i2c0_mipi1: i2c@57226000 {
+		compatible = "fsl,imx8qm-lpi2c", "fsl,imx7ulp-lpi2c";
+		reg = <0x57226000 0x1000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		interrupts = <8>;
+		interrupt-parent = <&irqsteer_mipi1>;
+		clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>,
+			 <&mipi1_i2c0_lpcg_ipg_clk IMX_LPCG_CLK_0>;
+		clock-names = "per", "ipg";
+		assigned-clocks = <&mipi1_i2c0_lpcg_clk IMX_LPCG_CLK_0>;
+		assigned-clock-rates = <24000000>;
+		power-domains = <&pd IMX_SC_R_MIPI_1_I2C_0>;
+		status = "disabled";
+	};
+};