| Message ID | 20240611015200.40996-1-minda.chen@starfivetech.com (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | [v1] riscv: dts: starfive: add PCIe dts configuration for JH7110 | expand |
On Tue, Jun 11, 2024 at 09:52:00AM +0800, Minda Chen wrote: > Add PCIe dts configuraion for JH7110 SoC platform. > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> > --- > .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ > 2 files changed, 150 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > index 8ff6ea64f048..1da7379f4e08 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > @@ -294,6 +294,22 @@ > status = "okay"; > }; > > +&pcie0 { > + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; > + phys = <&pciephy0>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie0_pins>; > + status = "okay"; > +}; > + > +&pcie1 { > + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; > + phys = <&pciephy1>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pcie1_pins>; > + status = "okay"; > +}; Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports exposed? I assume if one does, all does, since they're basically identical?
> > On Tue, Jun 11, 2024 at 09:52:00AM +0800, Minda Chen wrote: > > Add PCIe dts configuraion for JH7110 SoC platform. > > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> > > --- > > .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ > > arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ > > 2 files changed, 150 insertions(+) > > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > index 8ff6ea64f048..1da7379f4e08 100644 > > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > @@ -294,6 +294,22 @@ > > status = "okay"; > > }; > > > > +&pcie0 { > > + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; > > + phys = <&pciephy0>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie0_pins>; > > + status = "okay"; > > +}; > > + > > +&pcie1 { > > + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; > > + phys = <&pciephy1>; > > + pinctrl-names = "default"; > > + pinctrl-0 = <&pcie1_pins>; > > + status = "okay"; > > +}; > > Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports exposed? I > assume if one does, all does, since they're basically identical? Visionfive 2 and milkv mars are all the same. Star64 do NOT enable PCIe0, PCIe1 pins are the same.
On Wed, Jun 12, 2024 at 01:48:55AM +0000, Minda Chen wrote: > > > > > > On Tue, Jun 11, 2024 at 09:52:00AM +0800, Minda Chen wrote: > > > Add PCIe dts configuraion for JH7110 SoC platform. > > > > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > > > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> > > > --- > > > .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ > > > arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ > > > 2 files changed, 150 insertions(+) > > > > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > > b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > > index 8ff6ea64f048..1da7379f4e08 100644 > > > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > > @@ -294,6 +294,22 @@ > > > status = "okay"; > > > }; > > > > > > +&pcie0 { > > > + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; > > > + phys = <&pciephy0>; > > > + pinctrl-names = "default"; > > > + pinctrl-0 = <&pcie0_pins>; > > > + status = "okay"; > > > +}; > > > + > > > +&pcie1 { > > > + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; > > > + phys = <&pciephy1>; > > > + pinctrl-names = "default"; > > > + pinctrl-0 = <&pcie1_pins>; > > > + status = "okay"; > > > +}; > > > > Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports exposed? I > > assume if one does, all does, since they're basically identical? > > Visionfive 2 and milkv mars are all the same. Star64 do NOT enable PCIe0, PCIe1 pins are the same. This patch adds both PCIe instances for the Star64 though, since that also includes jh7110-common.dtsi. I think you need to enable these in the board dts files instead?
On 11 Jun 2024, at 02:52, Minda Chen <minda.chen@starfivetech.com> wrote: > > Add PCIe dts configuraion for JH7110 SoC platform. > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> > --- > .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ > arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ > 2 files changed, 150 insertions(+) Is there a corresponding YAML schema? Jess
On Wed, Jun 12, 2024 at 04:24:44PM +0100, Jessica Clarke wrote: > On 11 Jun 2024, at 02:52, Minda Chen <minda.chen@starfivetech.com> wrote: > > > > Add PCIe dts configuraion for JH7110 SoC platform. > > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> > > --- > > .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ > > arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 +++++++++++++++++++ > > 2 files changed, 150 insertions(+) > > Is there a corresponding YAML schema? Yeah, it's in linux-next via the PCI tree: https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/pci/starfive,jh7110-pcie.yaml
> > On Wed, Jun 12, 2024 at 01:48:55AM +0000, Minda Chen wrote: > > > > > > > > > > On Tue, Jun 11, 2024 at 09:52:00AM +0800, Minda Chen wrote: > > > > Add PCIe dts configuraion for JH7110 SoC platform. > > > > > > > > Signed-off-by: Minda Chen <minda.chen@starfivetech.com> > > > > Reviewed-by: Hal Feng <hal.feng@starfivetech.com> > > > > --- > > > > .../boot/dts/starfive/jh7110-common.dtsi | 64 ++++++++++++++ > > > > arch/riscv/boot/dts/starfive/jh7110.dtsi | 86 > +++++++++++++++++++ > > > > 2 files changed, 150 insertions(+) > > > > > > > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > > > b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > > > index 8ff6ea64f048..1da7379f4e08 100644 > > > > --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > > > +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi > > > > @@ -294,6 +294,22 @@ > > > > status = "okay"; > > > > }; > > > > > > > > +&pcie0 { > > > > + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; > > > > + phys = <&pciephy0>; > > > > + pinctrl-names = "default"; > > > > + pinctrl-0 = <&pcie0_pins>; > > > > + status = "okay"; > > > > +}; > > > > + > > > > +&pcie1 { > > > > + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; > > > > + phys = <&pciephy1>; > > > > + pinctrl-names = "default"; > > > > + pinctrl-0 = <&pcie1_pins>; > > > > + status = "okay"; > > > > +}; > > > > > > Do all 3 of the mars, star64 and visionfive 2 have both PCIe ports > > > exposed? I assume if one does, all does, since they're basically identical? > > > > Visionfive 2 and milkv mars are all the same. Star64 do NOT enable PCIe0, > PCIe1 pins are the same. > > This patch adds both PCIe instances for the Star64 though, since that also > includes jh7110-common.dtsi. I think you need to enable these in the board dts > files instead? OK. I will enable them in board dts file. Thanks.
diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi index 8ff6ea64f048..1da7379f4e08 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi @@ -294,6 +294,22 @@ status = "okay"; }; +&pcie0 { + perst-gpios = <&sysgpio 26 GPIO_ACTIVE_LOW>; + phys = <&pciephy0>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie0_pins>; + status = "okay"; +}; + +&pcie1 { + perst-gpios = <&sysgpio 28 GPIO_ACTIVE_LOW>; + phys = <&pciephy1>; + pinctrl-names = "default"; + pinctrl-0 = <&pcie1_pins>; + status = "okay"; +}; + &pwmdac { pinctrl-names = "default"; pinctrl-0 = <&pwmdac_pins>; @@ -476,6 +492,54 @@ }; }; + pcie0_pins: pcie0-0 { + clkreq-pins { + pinmux = <GPIOMUX(27, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = <GPIOMUX(32, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + + pcie1_pins: pcie1-0 { + clkreq-pins { + pinmux = <GPIOMUX(29, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-down; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + + wake-pins { + pinmux = <GPIOMUX(21, GPOUT_LOW, + GPOEN_DISABLE, + GPI_NONE)>; + bias-pull-up; + drive-strength = <2>; + input-enable; + input-schmitt-disable; + slew-rate = <0>; + }; + }; + pwmdac_pins: pwmdac-0 { pwmdac-pins { pinmux = <GPIOMUX(33, GPOUT_SYS_PWMDAC_LEFT, diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi index 18047195c600..5ac70759e0ab 100644 --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi @@ -1214,5 +1214,91 @@ #reset-cells = <1>; power-domains = <&pwrc JH7110_PD_VOUT>; }; + + pcie0: pcie@940000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0x40000000 0x0 0x1000000>, + <0x0 0x2b000000 0x0 0x100000>; + reg-names = "cfg", "apb"; + linux,pci-domain = <0>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0x0 0x30000000 0x0 0x30000000 0x0 0x08000000>, + <0xc3000000 0x9 0x00000000 0x9 0x00000000 0x0 0x40000000>; + interrupts = <56>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc0 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc0 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc0 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc0 0x4>; + msi-controller; + device_type = "pci"; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE0_TL>, + <&stgcrg JH7110_STGCLK_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE0_APB>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg JH7110_STGRST_PCIE0_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE0_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE0_BRG>, + <&stgcrg JH7110_STGRST_PCIE0_CORE>, + <&stgcrg JH7110_STGRST_PCIE0_APB>; + reset-names = "mst0", "slv0", "slv", "brg", + "core", "apb"; + status = "disabled"; + + pcie_intc0: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; + + pcie1: pcie@9c0000000 { + compatible = "starfive,jh7110-pcie"; + reg = <0x9 0xc0000000 0x0 0x1000000>, + <0x0 0x2c000000 0x0 0x100000>; + reg-names = "cfg", "apb"; + linux,pci-domain = <1>; + #address-cells = <3>; + #size-cells = <2>; + #interrupt-cells = <1>; + ranges = <0x82000000 0x0 0x38000000 0x0 0x38000000 0x0 0x08000000>, + <0xc3000000 0x9 0x80000000 0x9 0x80000000 0x0 0x40000000>; + interrupts = <57>; + interrupt-map-mask = <0x0 0x0 0x0 0x7>; + interrupt-map = <0x0 0x0 0x0 0x1 &pcie_intc1 0x1>, + <0x0 0x0 0x0 0x2 &pcie_intc1 0x2>, + <0x0 0x0 0x0 0x3 &pcie_intc1 0x3>, + <0x0 0x0 0x0 0x4 &pcie_intc1 0x4>; + msi-controller; + device_type = "pci"; + starfive,stg-syscon = <&stg_syscon>; + bus-range = <0x0 0xff>; + clocks = <&syscrg JH7110_SYSCLK_NOC_BUS_STG_AXI>, + <&stgcrg JH7110_STGCLK_PCIE1_TL>, + <&stgcrg JH7110_STGCLK_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGCLK_PCIE1_APB>; + clock-names = "noc", "tl", "axi_mst0", "apb"; + resets = <&stgcrg JH7110_STGRST_PCIE1_AXI_MST0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV0>, + <&stgcrg JH7110_STGRST_PCIE1_AXI_SLV>, + <&stgcrg JH7110_STGRST_PCIE1_BRG>, + <&stgcrg JH7110_STGRST_PCIE1_CORE>, + <&stgcrg JH7110_STGRST_PCIE1_APB>; + reset-names = "mst0", "slv0", "slv", "brg", + "core", "apb"; + status = "disabled"; + + pcie_intc1: interrupt-controller { + #address-cells = <0>; + #interrupt-cells = <1>; + interrupt-controller; + }; + }; }; };