| Message ID | 20240603111812.1514101-1-mark.rutland@arm.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | arm64: errata: Expand speculative SSBS workaround | expand |
On Mon, 03 Jun 2024 12:18:07 +0100, Mark Rutland wrote: > A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS > special-purpose register does not affect subsequent speculative > instructions, permitting speculative store bypassing for a window of > time. > > We recently addressed this for Cortex-X4 and Neoverse-V3: > > [...] Applied to arm64 (for-next/errata), thanks! [1/5] arm64: cputype: Add Cortex-X3 definitions https://git.kernel.org/arm64/c/be5a6f238700 [2/5] arm64: cputype: Add Cortex-A720 definitions https://git.kernel.org/arm64/c/add332c40328 [3/5] arm64: cputype: Add Cortex-X925 definitions https://git.kernel.org/arm64/c/fd2ff5f0b320 [4/5] arm64: errata: Unify speculative SSBS errata logic https://git.kernel.org/arm64/c/ec7687666080 [5/5] arm64: errata: Expand speculative SSBS workaround https://git.kernel.org/arm64/c/75b3c43eab59
Hi, A number of Arm Ltd CPUs suffer from errata whereby an MSR to the SSBS special-purpose register does not affect subsequent speculative instructions, permitting speculative store bypassing for a window of time. We recently addressed this for Cortex-X4 and Neoverse-V3: https://lore.kernel.org/linux-arm-kernel/20240508081400.235362-1-mark.rutland@arm.com/ ... which was merged into mainline in v6.10-rc1. Since then, Arm have published Software Developer Errata Notice (SDEN) documents for a number of CPUs affected by the same issue. This series updates the workaround to handle those CPUs. Since there are now a number of CPUs known to be affected, I've merged the Kconfig options to avoid duplicate text and boilerplate ifdeffery. Largely this is mechanical work to add the IDs and handle them for detection, but I have made two choices I'd like to check: * For the common Kconfig symbol I've used CONFIG_ARM64_ERRATUM_3194386 (matching the Neoverse-V3 erratum ID), following the example of CONFIG_ARM64_ERRATUM_1319367 which covers Cortex-A57 erratum 1319537 and Cortex-A72 erratum 1319367. Given the precedent, I'm assuming that's fine. I also considered ARM64_ERRATUM_SPECULATIVE_SSBS, but that required reflowing the table in the documentation, which is very churny. * I updated the runtime message to say: "SSBS not fully self-synchronizing", ... rather than listing every relevant erratum ID, as this would become very long: "ARM errata 3194386, 3312417, 3324334, 3324335, 3324336, 3324338, 3324339, 3456091" ... and if we end up needing to add more affected CPUs it would get even longer. I'm happy to use the latter if that's preferable. Mark. Mark Rutland (5): arm64: cputype: Add Cortex-X3 definitions arm64: cputype: Add Cortex-A720 definitions arm64: cputype: Add Cortex-X925 definitions arm64: errata: Unify speculative SSBS errata logic arm64: errata: Expand speculative SSBS workaround Documentation/arch/arm64/silicon-errata.rst | 16 ++++++++- arch/arm64/Kconfig | 36 +++++++-------------- arch/arm64/include/asm/cpucaps.h | 2 +- arch/arm64/include/asm/cputype.h | 6 ++++ arch/arm64/kernel/cpu_errata.c | 17 ++++++---- arch/arm64/kernel/proton-pack.c | 2 +- 6 files changed, 44 insertions(+), 35 deletions(-)