| Message ID | 20240614144552.2773592-1-maz@kernel.org (mailing list archive) |
|---|---|
| Headers | show |
| Series | KVM: arm64: nv: Shadow stage-2 page table handling | expand |
On Fri, 14 Jun 2024 15:45:36 +0100, Marc Zyngier wrote: > Here's the thurd version of the shadow stage-2 handling for NV > support on arm64. > > * From v2 [2] > > - Simplified the S2 walker by dropping a bunch of redundant > fields from the walker info structure > > [...] Applied to kvmarm/next, thanks! [01/16] KVM: arm64: nv: Support multiple nested Stage-2 mmu structures https://git.kernel.org/kvmarm/kvmarm/c/4f128f8e1aaa [02/16] KVM: arm64: nv: Implement nested Stage-2 page table walk logic https://git.kernel.org/kvmarm/kvmarm/c/61e30b9eef7f [03/16] KVM: arm64: nv: Handle shadow stage 2 page faults https://git.kernel.org/kvmarm/kvmarm/c/fd276e71d1e7 [04/16] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables https://git.kernel.org/kvmarm/kvmarm/c/ec14c272408a [05/16] KVM: arm64: nv: Add Stage-1 EL2 invalidation primitives https://git.kernel.org/kvmarm/kvmarm/c/82e86326ec58 [06/16] KVM: arm64: nv: Handle EL2 Stage-1 TLB invalidation https://git.kernel.org/kvmarm/kvmarm/c/67fda56e76da [07/16] KVM: arm64: nv: Handle TLB invalidation targeting L2 stage-1 https://git.kernel.org/kvmarm/kvmarm/c/8e236efa4cd2 [08/16] KVM: arm64: nv: Handle TLBI VMALLS12E1{,IS} operations https://git.kernel.org/kvmarm/kvmarm/c/e6c9a3015ff2 [09/16] KVM: arm64: nv: Handle TLBI ALLE1{,IS} operations https://git.kernel.org/kvmarm/kvmarm/c/5cfb6cec62f2 [10/16] KVM: arm64: nv: Handle TLBI IPAS2E1{,IS} operations https://git.kernel.org/kvmarm/kvmarm/c/70109bcd701e [11/16] KVM: arm64: nv: Handle FEAT_TTL hinted TLB operations https://git.kernel.org/kvmarm/kvmarm/c/d1de1576dc21 [12/16] KVM: arm64: nv: Tag shadow S2 entries with guest's leaf S2 level https://git.kernel.org/kvmarm/kvmarm/c/b1a3a94812b9 [13/16] KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information https://git.kernel.org/kvmarm/kvmarm/c/809b2e6013a5 [14/16] KVM: arm64: nv: Add handling of outer-shareable TLBI operations https://git.kernel.org/kvmarm/kvmarm/c/0cb8aae22676 [15/16] KVM: arm64: nv: Add handling of range-based TLBI operations https://git.kernel.org/kvmarm/kvmarm/c/5d476ca57d7d [16/16] KVM: arm64: nv: Add handling of NXS-flavoured TLBI operations https://git.kernel.org/kvmarm/kvmarm/c/0feec7769a63 -- Best, Oliver
Hi Marc, On 19-06-2024 02:11 pm, Oliver Upton wrote: > On Fri, 14 Jun 2024 15:45:36 +0100, Marc Zyngier wrote: >> Here's the thurd version of the shadow stage-2 handling for NV >> support on arm64. >> >> * From v2 [2] >> >> - Simplified the S2 walker by dropping a bunch of redundant >> fields from the walker info structure >> >> [...] > > Applied to kvmarm/next, thanks! > > [01/16] KVM: arm64: nv: Support multiple nested Stage-2 mmu structures > https://git.kernel.org/kvmarm/kvmarm/c/4f128f8e1aaa > [02/16] KVM: arm64: nv: Implement nested Stage-2 page table walk logic > https://git.kernel.org/kvmarm/kvmarm/c/61e30b9eef7f > [03/16] KVM: arm64: nv: Handle shadow stage 2 page faults > https://git.kernel.org/kvmarm/kvmarm/c/fd276e71d1e7 > [04/16] KVM: arm64: nv: Unmap/flush shadow stage 2 page tables > https://git.kernel.org/kvmarm/kvmarm/c/ec14c272408a > [05/16] KVM: arm64: nv: Add Stage-1 EL2 invalidation primitives > https://git.kernel.org/kvmarm/kvmarm/c/82e86326ec58 > [06/16] KVM: arm64: nv: Handle EL2 Stage-1 TLB invalidation > https://git.kernel.org/kvmarm/kvmarm/c/67fda56e76da > [07/16] KVM: arm64: nv: Handle TLB invalidation targeting L2 stage-1 > https://git.kernel.org/kvmarm/kvmarm/c/8e236efa4cd2 > [08/16] KVM: arm64: nv: Handle TLBI VMALLS12E1{,IS} operations > https://git.kernel.org/kvmarm/kvmarm/c/e6c9a3015ff2 > [09/16] KVM: arm64: nv: Handle TLBI ALLE1{,IS} operations > https://git.kernel.org/kvmarm/kvmarm/c/5cfb6cec62f2 > [10/16] KVM: arm64: nv: Handle TLBI IPAS2E1{,IS} operations > https://git.kernel.org/kvmarm/kvmarm/c/70109bcd701e > [11/16] KVM: arm64: nv: Handle FEAT_TTL hinted TLB operations > https://git.kernel.org/kvmarm/kvmarm/c/d1de1576dc21 > [12/16] KVM: arm64: nv: Tag shadow S2 entries with guest's leaf S2 level > https://git.kernel.org/kvmarm/kvmarm/c/b1a3a94812b9 > [13/16] KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information > https://git.kernel.org/kvmarm/kvmarm/c/809b2e6013a5 > [14/16] KVM: arm64: nv: Add handling of outer-shareable TLBI operations > https://git.kernel.org/kvmarm/kvmarm/c/0cb8aae22676 > [15/16] KVM: arm64: nv: Add handling of range-based TLBI operations > https://git.kernel.org/kvmarm/kvmarm/c/5d476ca57d7d > [16/16] KVM: arm64: nv: Add handling of NXS-flavoured TLBI operations > https://git.kernel.org/kvmarm/kvmarm/c/0feec7769a63 > > -- > Best, > Oliver IIRC, Most of the patches that are specific to NV have been merged upstream. However I do see that, some of the vGIC and Timer related patches are still in your private NV repository. Can these patches be prioritized to upstream, so that we can have have the first working version of NV on mainline.
On Thu, 21 Nov 2024 08:11:00 +0000, Ganapatrao Kulkarni <gankulkarni@os.amperecomputing.com> wrote: Hi Ganapatrao, > IIRC, Most of the patches that are specific to NV have been merged > upstream. However I do see that, some of the vGIC and Timer related > patches are still in your private NV repository. Can these patches be > prioritized to upstream, so that we can have have the first working > version of NV on mainline. Who is *we*? Things get upstreamed when we (people doing the actual work) decide they are ready. At the moment, they are not. Also, while I enjoy working on NV, this isn't *my* priority. Thanks, M.
Here's the thurd version of the shadow stage-2 handling for NV support on arm64. * From v2 [2] - Simplified the S2 walker by dropping a bunch of redundant fields from the walker info structure - Added some more lockdep assertions (Oliver) - Added more precise comments for the TTL-like annotations in the shadow S2 (Oliver) * From v1 [1] - Reworked the allocation of shadow S2 structures at init time to be slightly clearer - Lots of small cleanups - Rebased on v6.10-rc1 [1] https://lore.kernel.org/r/20240409175448.3507472-1-maz@kernel.org Christoffer Dall (2): KVM: arm64: nv: Implement nested Stage-2 page table walk logic KVM: arm64: nv: Unmap/flush shadow stage 2 page tables Marc Zyngier (14): KVM: arm64: nv: Support multiple nested Stage-2 mmu structures KVM: arm64: nv: Handle shadow stage 2 page faults KVM: arm64: nv: Add Stage-1 EL2 invalidation primitives KVM: arm64: nv: Handle EL2 Stage-1 TLB invalidation KVM: arm64: nv: Handle TLB invalidation targeting L2 stage-1 KVM: arm64: nv: Handle TLBI VMALLS12E1{,IS} operations KVM: arm64: nv: Handle TLBI ALLE1{,IS} operations KVM: arm64: nv: Handle TLBI IPAS2E1{,IS} operations KVM: arm64: nv: Handle FEAT_TTL hinted TLB operations KVM: arm64: nv: Tag shadow S2 entries with guest's leaf S2 level KVM: arm64: nv: Invalidate TLBs based on shadow S2 TTL-like information KVM: arm64: nv: Add handling of outer-shareable TLBI operations KVM: arm64: nv: Add handling of range-based TLBI operations KVM: arm64: nv: Add handling of NXS-flavoured TLBI operations arch/arm64/include/asm/esr.h | 1 + arch/arm64/include/asm/kvm_asm.h | 2 + arch/arm64/include/asm/kvm_host.h | 36 ++ arch/arm64/include/asm/kvm_mmu.h | 26 + arch/arm64/include/asm/kvm_nested.h | 127 +++++ arch/arm64/include/asm/sysreg.h | 17 + arch/arm64/kvm/arm.c | 11 + arch/arm64/kvm/hyp/vhe/switch.c | 51 +- arch/arm64/kvm/hyp/vhe/tlb.c | 147 ++++++ arch/arm64/kvm/mmu.c | 213 ++++++-- arch/arm64/kvm/nested.c | 781 +++++++++++++++++++++++++++- arch/arm64/kvm/reset.c | 6 + arch/arm64/kvm/sys_regs.c | 398 ++++++++++++++ 13 files changed, 1775 insertions(+), 41 deletions(-)