| Message ID | 20240617131425.7526-3-cuiyunhui@bytedance.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 66381d36771e4ffedbea0dd23da17cf3d38e9aae |
| Headers | show |
| Series | [v6,1/3] riscv: cacheinfo: remove the useless input parameter (node) of ci_leaf_init() | expand |
Hi Sunil, On Mon, Jun 17, 2024 at 9:14 PM Yunhui Cui <cuiyunhui@bytedance.com> wrote: > > After adding ACPI support to populate_cache_leaves(), RISC-V can build > cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT > configuration. > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> > Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> > Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> > --- > arch/riscv/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 9f38a5ecbee3..1b4c310a59fb 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -13,6 +13,7 @@ config 32BIT > config RISCV > def_bool y > select ACPI_GENERIC_GSI if ACPI > + select ACPI_PPTT if ACPI > select ACPI_REDUCED_HARDWARE_ONLY if ACPI > select ARCH_DMA_DEFAULT_COHERENT > select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION > -- > 2.20.1 > Gentle ping. Thanks, Yunhui
On Wed, Jun 19, 2024 at 07:32:18PM +0800, yunhui cui wrote: > Hi Sunil, > > On Mon, Jun 17, 2024 at 9:14 PM Yunhui Cui <cuiyunhui@bytedance.com> wrote: > > > > After adding ACPI support to populate_cache_leaves(), RISC-V can build > > cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT > > configuration. > > > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> > > Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> > > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> > > Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> > > --- > > arch/riscv/Kconfig | 1 + > > 1 file changed, 1 insertion(+) > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > index 9f38a5ecbee3..1b4c310a59fb 100644 > > --- a/arch/riscv/Kconfig > > +++ b/arch/riscv/Kconfig > > @@ -13,6 +13,7 @@ config 32BIT > > config RISCV > > def_bool y > > select ACPI_GENERIC_GSI if ACPI > > + select ACPI_PPTT if ACPI > > select ACPI_REDUCED_HARDWARE_ONLY if ACPI > > select ARCH_DMA_DEFAULT_COHERENT > > select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION > > -- > > 2.20.1 > > > > Gentle ping. > Actually, my RB is still valid. Anyway, here again. Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> Thanks, Sunil
Hi Sunil, On Wed, Jun 19, 2024 at 9:11 PM Sunil V L <sunilvl@ventanamicro.com> wrote: > > On Wed, Jun 19, 2024 at 07:32:18PM +0800, yunhui cui wrote: > > Hi Sunil, > > > > On Mon, Jun 17, 2024 at 9:14 PM Yunhui Cui <cuiyunhui@bytedance.com> wrote: > > > > > > After adding ACPI support to populate_cache_leaves(), RISC-V can build > > > cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT > > > configuration. > > > > > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> > > > Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> > > > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> > > > Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> > > > --- > > > arch/riscv/Kconfig | 1 + > > > 1 file changed, 1 insertion(+) > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > > index 9f38a5ecbee3..1b4c310a59fb 100644 > > > --- a/arch/riscv/Kconfig > > > +++ b/arch/riscv/Kconfig > > > @@ -13,6 +13,7 @@ config 32BIT > > > config RISCV > > > def_bool y > > > select ACPI_GENERIC_GSI if ACPI > > > + select ACPI_PPTT if ACPI > > > select ACPI_REDUCED_HARDWARE_ONLY if ACPI > > > select ARCH_DMA_DEFAULT_COHERENT > > > select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION > > > -- > > > 2.20.1 > > > > > > > Gentle ping. > > > Actually, my RB is still valid. Anyway, here again. > > Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> > > Thanks, > Sunil Okay, thank you. BTW, when will this patchset be picked up to linux-next? Thanks, Yunhui
On Thu, Jun 20, 2024 at 09:28:18AM +0800, yunhui cui wrote: > Hi Sunil, > > On Wed, Jun 19, 2024 at 9:11 PM Sunil V L <sunilvl@ventanamicro.com> wrote: > > > > On Wed, Jun 19, 2024 at 07:32:18PM +0800, yunhui cui wrote: > > > Hi Sunil, > > > > > > On Mon, Jun 17, 2024 at 9:14 PM Yunhui Cui <cuiyunhui@bytedance.com> wrote: > > > > > > > > After adding ACPI support to populate_cache_leaves(), RISC-V can build > > > > cacheinfo through the ACPI PPTT table, thus enabling the ACPI_PPTT > > > > configuration. > > > > > > > > Signed-off-by: Yunhui Cui <cuiyunhui@bytedance.com> > > > > Reviewed-by: Jeremy Linton <jeremy.linton@arm.com> > > > > Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> > > > > Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> > > > > --- > > > > arch/riscv/Kconfig | 1 + > > > > 1 file changed, 1 insertion(+) > > > > > > > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > > > > index 9f38a5ecbee3..1b4c310a59fb 100644 > > > > --- a/arch/riscv/Kconfig > > > > +++ b/arch/riscv/Kconfig > > > > @@ -13,6 +13,7 @@ config 32BIT > > > > config RISCV > > > > def_bool y > > > > select ACPI_GENERIC_GSI if ACPI > > > > + select ACPI_PPTT if ACPI > > > > select ACPI_REDUCED_HARDWARE_ONLY if ACPI > > > > select ARCH_DMA_DEFAULT_COHERENT > > > > select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION > > > > -- > > > > 2.20.1 > > > > > > > > > > Gentle ping. > > > > > Actually, my RB is still valid. Anyway, here again. > > > > Reviewed-by: Sunil V L <sunilvl@ventanamicro.com> > > > > Thanks, > > Sunil > > Okay, thank you. BTW, when will this patchset be picked up to linux-next? > Hi Palmer, Can this series be picked up for -next? Looks like it has got sufficient reviews. Thanks, Sunil
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 9f38a5ecbee3..1b4c310a59fb 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -13,6 +13,7 @@ config 32BIT config RISCV def_bool y select ACPI_GENERIC_GSI if ACPI + select ACPI_PPTT if ACPI select ACPI_REDUCED_HARDWARE_ONLY if ACPI select ARCH_DMA_DEFAULT_COHERENT select ARCH_ENABLE_HUGEPAGE_MIGRATION if HUGETLB_PAGE && MIGRATION