| Message ID | 20240503130147.1154804-11-joey.gouly@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: Permission Overlay Extension | expand |
On Fri, May 03, 2024 at 02:01:28PM +0100, Joey Gouly wrote: > Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to > check if the CPU supports the feature. > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
On 5/3/24 18:31, Joey Gouly wrote: > Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to > check if the CPU supports the feature. > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > --- > > This takes the last bit of HWCAP2, is this fine? What can we do about more features in the future? > > > Documentation/arch/arm64/elf_hwcaps.rst | 2 ++ > arch/arm64/include/asm/hwcap.h | 1 + > arch/arm64/include/uapi/asm/hwcap.h | 1 + > arch/arm64/kernel/cpufeature.c | 14 ++++++++++++++ > arch/arm64/kernel/cpuinfo.c | 1 + > 5 files changed, 19 insertions(+) > > diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst > index 448c1664879b..694f67fa07d1 100644 > --- a/Documentation/arch/arm64/elf_hwcaps.rst > +++ b/Documentation/arch/arm64/elf_hwcaps.rst > @@ -365,6 +365,8 @@ HWCAP2_SME_SF8DP2 > HWCAP2_SME_SF8DP4 > Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. > > +HWCAP2_POE > + Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001. > > 4. Unused AT_HWCAP bits > ----------------------- > diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h > index 4edd3b61df11..a775adddecf2 100644 > --- a/arch/arm64/include/asm/hwcap.h > +++ b/arch/arm64/include/asm/hwcap.h > @@ -157,6 +157,7 @@ > #define KERNEL_HWCAP_SME_SF8FMA __khwcap2_feature(SME_SF8FMA) > #define KERNEL_HWCAP_SME_SF8DP4 __khwcap2_feature(SME_SF8DP4) > #define KERNEL_HWCAP_SME_SF8DP2 __khwcap2_feature(SME_SF8DP2) > +#define KERNEL_HWCAP_POE __khwcap2_feature(POE) > > /* > * This yields a mask that user programs can use to figure out what > diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h > index 285610e626f5..055381b2c615 100644 > --- a/arch/arm64/include/uapi/asm/hwcap.h > +++ b/arch/arm64/include/uapi/asm/hwcap.h > @@ -122,5 +122,6 @@ > #define HWCAP2_SME_SF8FMA (1UL << 60) > #define HWCAP2_SME_SF8DP4 (1UL << 61) > #define HWCAP2_SME_SF8DP2 (1UL << 62) > +#define HWCAP2_POE (1UL << 63) > > #endif /* _UAPI__ASM_HWCAP_H */ > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 2f3c2346e156..8c02aae9db11 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -465,6 +465,8 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { > }; > > static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { > + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), > + FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), > ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), > ARM64_FTR_END, > @@ -2339,6 +2341,14 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) > sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); > } > > +#ifdef CONFIG_ARM64_POE > +static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) > +{ > + sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE); > + sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE); > +} > +#endif > + > /* Internal helper functions to match cpu capability type */ > static bool > cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) > @@ -2867,6 +2877,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { > .capability = ARM64_HAS_S1POE, > .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, > .matches = has_cpuid_feature, > + .cpu_enable = cpu_enable_poe, > ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) > }, > #endif > @@ -3034,6 +3045,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { > HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), > HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), > HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), > +#ifdef CONFIG_ARM64_POE > + HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), > +#endif > {}, > }; > > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > index 09eeaa24d456..b9db812082b3 100644 > --- a/arch/arm64/kernel/cpuinfo.c > +++ b/arch/arm64/kernel/cpuinfo.c > @@ -143,6 +143,7 @@ static const char *const hwcap_str[] = { > [KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma", > [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4", > [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2", > + [KERNEL_HWCAP_POE] = "poe", > }; > > #ifdef CONFIG_COMPAT This LGTM but as Joey mentioned earlier, what happens when another new feature gets added later which needs to be exposed to userspace, add HWCAP3 ? Reviewed-by: Anshuman Khandual <anshuman.khandual@arm.com>
On Fri, May 03, 2024 at 02:01:28PM +0100, Joey Gouly wrote: > This takes the last bit of HWCAP2, is this fine? What can we do about > more features in the future? HWCAP3 has already been allocated so we could just start using that.
On Fri, May 03, 2024 at 02:01:28PM +0100, Joey Gouly wrote: > Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to > check if the CPU supports the feature. > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > Cc: Catalin Marinas <catalin.marinas@arm.com> > Cc: Will Deacon <will@kernel.org> > --- > > This takes the last bit of HWCAP2, is this fine? What can we do about more features in the future? > > > Documentation/arch/arm64/elf_hwcaps.rst | 2 ++ > arch/arm64/include/asm/hwcap.h | 1 + > arch/arm64/include/uapi/asm/hwcap.h | 1 + > arch/arm64/kernel/cpufeature.c | 14 ++++++++++++++ > arch/arm64/kernel/cpuinfo.c | 1 + > 5 files changed, 19 insertions(+) > > diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst > index 448c1664879b..694f67fa07d1 100644 > --- a/Documentation/arch/arm64/elf_hwcaps.rst > +++ b/Documentation/arch/arm64/elf_hwcaps.rst > @@ -365,6 +365,8 @@ HWCAP2_SME_SF8DP2 > HWCAP2_SME_SF8DP4 > Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. > > +HWCAP2_POE > + Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001. Nit: unintentionally dropped blank line before the section heading? > > 4. Unused AT_HWCAP bits > ----------------------- [...] Cheers ---Dave
On Thu, Jul 25, 2024 at 04:49:08PM +0100, Dave Martin wrote: > On Fri, May 03, 2024 at 02:01:28PM +0100, Joey Gouly wrote: > > Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to > > check if the CPU supports the feature. > > > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > Cc: Will Deacon <will@kernel.org> > > --- > > > > This takes the last bit of HWCAP2, is this fine? What can we do about more features in the future? > > > > > > Documentation/arch/arm64/elf_hwcaps.rst | 2 ++ > > arch/arm64/include/asm/hwcap.h | 1 + > > arch/arm64/include/uapi/asm/hwcap.h | 1 + > > arch/arm64/kernel/cpufeature.c | 14 ++++++++++++++ > > arch/arm64/kernel/cpuinfo.c | 1 + > > 5 files changed, 19 insertions(+) > > > > diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst > > index 448c1664879b..694f67fa07d1 100644 > > --- a/Documentation/arch/arm64/elf_hwcaps.rst > > +++ b/Documentation/arch/arm64/elf_hwcaps.rst > > @@ -365,6 +365,8 @@ HWCAP2_SME_SF8DP2 > > HWCAP2_SME_SF8DP4 > > Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. > > > > +HWCAP2_POE > > + Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001. > > Nit: unintentionally dropped blank line before the section heading? Now there's only one blank line, I think c1932cac7902a8b0f7355515917dedc5412eb15d unintentionally added 2 blank lines, before that it was always 1! > > > > > 4. Unused AT_HWCAP bits > > ----------------------- > > [...] > > Cheers > ---Dave
On Thu, Aug 01, 2024 at 05:04:03PM +0100, Joey Gouly wrote: > On Thu, Jul 25, 2024 at 04:49:08PM +0100, Dave Martin wrote: > > On Fri, May 03, 2024 at 02:01:28PM +0100, Joey Gouly wrote: > > > Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to > > > check if the CPU supports the feature. > > > > > > Signed-off-by: Joey Gouly <joey.gouly@arm.com> > > > Cc: Catalin Marinas <catalin.marinas@arm.com> > > > Cc: Will Deacon <will@kernel.org> > > > --- > > > > > > This takes the last bit of HWCAP2, is this fine? What can we do about more features in the future? > > > > > > > > > Documentation/arch/arm64/elf_hwcaps.rst | 2 ++ > > > arch/arm64/include/asm/hwcap.h | 1 + > > > arch/arm64/include/uapi/asm/hwcap.h | 1 + > > > arch/arm64/kernel/cpufeature.c | 14 ++++++++++++++ > > > arch/arm64/kernel/cpuinfo.c | 1 + > > > 5 files changed, 19 insertions(+) > > > > > > diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst > > > index 448c1664879b..694f67fa07d1 100644 > > > --- a/Documentation/arch/arm64/elf_hwcaps.rst > > > +++ b/Documentation/arch/arm64/elf_hwcaps.rst > > > @@ -365,6 +365,8 @@ HWCAP2_SME_SF8DP2 > > > HWCAP2_SME_SF8DP4 > > > Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. > > > > > > +HWCAP2_POE > > > + Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001. > > > > Nit: unintentionally dropped blank line before the section heading? > > Now there's only one blank line, I think > c1932cac7902a8b0f7355515917dedc5412eb15d unintentionally added 2 blank lines, > before that it was always 1! Hmmm, true. Not a big deal, I guess. Cheers ---Dave
diff --git a/Documentation/arch/arm64/elf_hwcaps.rst b/Documentation/arch/arm64/elf_hwcaps.rst index 448c1664879b..694f67fa07d1 100644 --- a/Documentation/arch/arm64/elf_hwcaps.rst +++ b/Documentation/arch/arm64/elf_hwcaps.rst @@ -365,6 +365,8 @@ HWCAP2_SME_SF8DP2 HWCAP2_SME_SF8DP4 Functionality implied by ID_AA64SMFR0_EL1.SF8DP4 == 0b1. +HWCAP2_POE + Functionality implied by ID_AA64MMFR3_EL1.S1POE == 0b0001. 4. Unused AT_HWCAP bits ----------------------- diff --git a/arch/arm64/include/asm/hwcap.h b/arch/arm64/include/asm/hwcap.h index 4edd3b61df11..a775adddecf2 100644 --- a/arch/arm64/include/asm/hwcap.h +++ b/arch/arm64/include/asm/hwcap.h @@ -157,6 +157,7 @@ #define KERNEL_HWCAP_SME_SF8FMA __khwcap2_feature(SME_SF8FMA) #define KERNEL_HWCAP_SME_SF8DP4 __khwcap2_feature(SME_SF8DP4) #define KERNEL_HWCAP_SME_SF8DP2 __khwcap2_feature(SME_SF8DP2) +#define KERNEL_HWCAP_POE __khwcap2_feature(POE) /* * This yields a mask that user programs can use to figure out what diff --git a/arch/arm64/include/uapi/asm/hwcap.h b/arch/arm64/include/uapi/asm/hwcap.h index 285610e626f5..055381b2c615 100644 --- a/arch/arm64/include/uapi/asm/hwcap.h +++ b/arch/arm64/include/uapi/asm/hwcap.h @@ -122,5 +122,6 @@ #define HWCAP2_SME_SF8FMA (1UL << 60) #define HWCAP2_SME_SF8DP4 (1UL << 61) #define HWCAP2_SME_SF8DP2 (1UL << 62) +#define HWCAP2_POE (1UL << 63) #endif /* _UAPI__ASM_HWCAP_H */ diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index 2f3c2346e156..8c02aae9db11 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -465,6 +465,8 @@ static const struct arm64_ftr_bits ftr_id_aa64mmfr2[] = { }; static const struct arm64_ftr_bits ftr_id_aa64mmfr3[] = { + ARM64_FTR_BITS(FTR_VISIBLE_IF_IS_ENABLED(CONFIG_ARM64_POE), + FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1POE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_S1PIE_SHIFT, 4, 0), ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64MMFR3_EL1_TCRX_SHIFT, 4, 0), ARM64_FTR_END, @@ -2339,6 +2341,14 @@ static void cpu_enable_mops(const struct arm64_cpu_capabilities *__unused) sysreg_clear_set(sctlr_el1, 0, SCTLR_EL1_MSCEn); } +#ifdef CONFIG_ARM64_POE +static void cpu_enable_poe(const struct arm64_cpu_capabilities *__unused) +{ + sysreg_clear_set(REG_TCR2_EL1, 0, TCR2_EL1x_E0POE); + sysreg_clear_set(CPACR_EL1, 0, CPACR_ELx_E0POE); +} +#endif + /* Internal helper functions to match cpu capability type */ static bool cpucap_late_cpu_optional(const struct arm64_cpu_capabilities *cap) @@ -2867,6 +2877,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = { .capability = ARM64_HAS_S1POE, .type = ARM64_CPUCAP_BOOT_CPU_FEATURE, .matches = has_cpuid_feature, + .cpu_enable = cpu_enable_poe, ARM64_CPUID_FIELDS(ID_AA64MMFR3_EL1, S1POE, IMP) }, #endif @@ -3034,6 +3045,9 @@ static const struct arm64_cpu_capabilities arm64_elf_hwcaps[] = { HWCAP_CAP(ID_AA64FPFR0_EL1, F8DP2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8DP2), HWCAP_CAP(ID_AA64FPFR0_EL1, F8E4M3, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E4M3), HWCAP_CAP(ID_AA64FPFR0_EL1, F8E5M2, IMP, CAP_HWCAP, KERNEL_HWCAP_F8E5M2), +#ifdef CONFIG_ARM64_POE + HWCAP_CAP(ID_AA64MMFR3_EL1, S1POE, IMP, CAP_HWCAP, KERNEL_HWCAP_POE), +#endif {}, }; diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c index 09eeaa24d456..b9db812082b3 100644 --- a/arch/arm64/kernel/cpuinfo.c +++ b/arch/arm64/kernel/cpuinfo.c @@ -143,6 +143,7 @@ static const char *const hwcap_str[] = { [KERNEL_HWCAP_SME_SF8FMA] = "smesf8fma", [KERNEL_HWCAP_SME_SF8DP4] = "smesf8dp4", [KERNEL_HWCAP_SME_SF8DP2] = "smesf8dp2", + [KERNEL_HWCAP_POE] = "poe", }; #ifdef CONFIG_COMPAT
Expose a HWCAP and ID_AA64MMFR3_EL1_S1POE to userspace, so they can be used to check if the CPU supports the feature. Signed-off-by: Joey Gouly <joey.gouly@arm.com> Cc: Catalin Marinas <catalin.marinas@arm.com> Cc: Will Deacon <will@kernel.org> --- This takes the last bit of HWCAP2, is this fine? What can we do about more features in the future? Documentation/arch/arm64/elf_hwcaps.rst | 2 ++ arch/arm64/include/asm/hwcap.h | 1 + arch/arm64/include/uapi/asm/hwcap.h | 1 + arch/arm64/kernel/cpufeature.c | 14 ++++++++++++++ arch/arm64/kernel/cpuinfo.c | 1 + 5 files changed, 19 insertions(+)