| Message ID | 20240511104341.151550-4-aleksandar.rikalo@syrmia.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | MIPS: Support I6500 multi-cluster configuration | expand |
On Sat, May 11 2024 at 12:43, Aleksandar Rikalo wrote: > A few pieces of code in the MIPS GIC driver operate on the GIC local > register block for each online CPU, accessing each via the GIC's > other/redirect register block. This patch abstracts the process of > iterating over online CPUs & configuring the other/redirect region to > access their registers through a new for_each_online_cpu_gic() macro. > > This simplifies users of the new macro slightly, and more importantly > prepares us for handling multi-cluster systems where the register > configuration will be done via the CM's GCR_CL_REDIRECT register. By > abstracting all other/redirect block configuration through this macro, > and the __gic_with_next_online_cpu() function which backs it, users will > trivially gain support for multi-cluster when it is implemented in > __gic_with_next_online_cpu(). Can you please rework the change log according to https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#changelog > Signed-off-by: Paul Burton <paulburton@kernel.org> > Signed-off-by: Chao-ying Fu <cfu@wavecomp.com> > Signed-off-by: Dragan Mladjenovic <dragan.mladjenovic@syrmia.com> > Signed-off-by: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> > --- > drivers/irqchip/irq-mips-gic.c | 61 +++++++++++++++++++++++++++++----- > 1 file changed, 52 insertions(+), 9 deletions(-) > > diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c > index 76253e864f23..9e7182150b5c 100644 > --- a/drivers/irqchip/irq-mips-gic.c > +++ b/drivers/irqchip/irq-mips-gic.c > @@ -66,6 +66,52 @@ static struct gic_all_vpes_chip_data { > bool mask; > } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; > > +static int __gic_with_next_online_cpu(int prev) > +{ > + unsigned int cpu; > + > + /* Discover the next online CPU */ > + cpu = cpumask_next(prev, cpu_online_mask); > + > + /* If there isn't one, we're done */ > + if (cpu >= nr_cpu_ids) > + return cpu; > + > + /* > + * Lock access to the next CPU's GIC local register block. > + * > + * In the single cluster case we simply set GIC_VL_OTHER. The caller > + * holds gic_lock so nothing can clobber the value we write. > + */ > + write_gic_vl_other(mips_cm_vp_id(cpu)); What unlocks the access? I assume it's magic, but then magic wants to be documented. > + > + return cpu; > +} > + > +static inline void __lockdep_assert_held(raw_spinlock_t *gic_lock) > +{ > + lockdep_assert_held(gic_lock); > +} What is exactly the point of this indirection? > +/** > + * for_each_online_cpu_gic() - Iterate over online CPUs, access local registers > + * @cpu: An integer variable to hold the current CPU number > + * @gic_lock: A pointer to raw spin lock used as a guard > + * > + * Iterate over online CPUs & configure the other/redirect register region to > + * access each CPUs GIC local register block, which can be accessed from the > + * loop body using read_gic_vo_*() or write_gic_vo_*() accessor functions or > + * their derivatives. > + * > + * The caller must hold gic_lock throughout the loop, such that GIC_VL_OTHER > + * cannot be clobbered. > + */ > +#define for_each_online_cpu_gic(cpu, gic_lock) \ > + for (__lockdep_assert_held(gic_lock), \ > + (cpu) = __gic_with_next_online_cpu(-1); \ > + (cpu) = __gic_with_next_online_cpu(cpu), \ > + (cpu) < nr_cpu_ids;) That's broken. It resolves to: for (cpu = foo(-1); cpu = foo(cpu), cpu < nr_cpu_ids; ) So on entering the loop: cpu = foo(-1); -> cpu == 0 Now it has to evaluate the loop condition which does: cpu = foo(cpu) -> cpu == 1 ... So CPU 0 is skipped unconditionally. No? Aside of that. Instead of this __lockdep_assert_held() obfuscation you can simply do: #define for_each_online_cpu_gic(cpu, gic_lock) \ guard(raw_spinlock_irqsave)(gic_lock); \ for ((cpu) = __gic_with_next_online_cpu(-1); \ (cpu) < nr_cpu_ids; \ (cpu) = __gic_with_next_online_cpu(cpu);) which simplifies the callsites even further. Thanks, tglx
diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c index 76253e864f23..9e7182150b5c 100644 --- a/drivers/irqchip/irq-mips-gic.c +++ b/drivers/irqchip/irq-mips-gic.c @@ -66,6 +66,52 @@ static struct gic_all_vpes_chip_data { bool mask; } gic_all_vpes_chip_data[GIC_NUM_LOCAL_INTRS]; +static int __gic_with_next_online_cpu(int prev) +{ + unsigned int cpu; + + /* Discover the next online CPU */ + cpu = cpumask_next(prev, cpu_online_mask); + + /* If there isn't one, we're done */ + if (cpu >= nr_cpu_ids) + return cpu; + + /* + * Lock access to the next CPU's GIC local register block. + * + * In the single cluster case we simply set GIC_VL_OTHER. The caller + * holds gic_lock so nothing can clobber the value we write. + */ + write_gic_vl_other(mips_cm_vp_id(cpu)); + + return cpu; +} + +static inline void __lockdep_assert_held(raw_spinlock_t *gic_lock) +{ + lockdep_assert_held(gic_lock); +} + +/** + * for_each_online_cpu_gic() - Iterate over online CPUs, access local registers + * @cpu: An integer variable to hold the current CPU number + * @gic_lock: A pointer to raw spin lock used as a guard + * + * Iterate over online CPUs & configure the other/redirect register region to + * access each CPUs GIC local register block, which can be accessed from the + * loop body using read_gic_vo_*() or write_gic_vo_*() accessor functions or + * their derivatives. + * + * The caller must hold gic_lock throughout the loop, such that GIC_VL_OTHER + * cannot be clobbered. + */ +#define for_each_online_cpu_gic(cpu, gic_lock) \ + for (__lockdep_assert_held(gic_lock), \ + (cpu) = __gic_with_next_online_cpu(-1); \ + (cpu) = __gic_with_next_online_cpu(cpu), \ + (cpu) < nr_cpu_ids;) + static void gic_clear_pcpu_masks(unsigned int intr) { unsigned int i; @@ -358,10 +404,9 @@ static void gic_mask_local_irq_all_vpes(struct irq_data *d) cd->mask = false; raw_spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + for_each_online_cpu_gic(cpu, &gic_lock) write_gic_vo_rmask(BIT(intr)); - } + raw_spin_unlock_irqrestore(&gic_lock, flags); } @@ -376,10 +421,9 @@ static void gic_unmask_local_irq_all_vpes(struct irq_data *d) cd->mask = true; raw_spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + for_each_online_cpu_gic(cpu, &gic_lock) write_gic_vo_smask(BIT(intr)); - } + raw_spin_unlock_irqrestore(&gic_lock, flags); } @@ -534,10 +578,9 @@ static int gic_irq_domain_map(struct irq_domain *d, unsigned int virq, return -EPERM; raw_spin_lock_irqsave(&gic_lock, flags); - for_each_online_cpu(cpu) { - write_gic_vl_other(mips_cm_vp_id(cpu)); + for_each_online_cpu_gic(cpu, &gic_lock) write_gic_vo_map(mips_gic_vx_map_reg(intr), map); - } + raw_spin_unlock_irqrestore(&gic_lock, flags); return 0;