diff mbox series

[3/4] PCI: mediatek-gen3: rely on reset_bulk APIs for phy reset lines

Message ID e8ab615a56759a4832833211257d83f56bf64303.1718980864.git.lorenzo@kernel.org (mailing list archive)
State New
Headers show
Series Add Airoha EN7581 PCIE support | expand

Commit Message

Lorenzo Bianconi June 21, 2024, 2:48 p.m. UTC 
Use reset_bulk APIs to manage phy reset lines. This is a preliminary
patch in order to add Airoha EN7581 pcie support.

Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
---
 drivers/pci/controller/pcie-mediatek-gen3.c | 49 ++++++++++++++++-----
 1 file changed, 37 insertions(+), 12 deletions(-)

Comments

Bjorn Helgaas June 21, 2024, 5:51 p.m. UTC | #1 
On Fri, Jun 21, 2024 at 04:48:49PM +0200, Lorenzo Bianconi wrote:
> Use reset_bulk APIs to manage phy reset lines. This is a preliminary
> patch in order to add Airoha EN7581 pcie support.

If you have occasion to revise this:

  s/rely/Rely/ in subject
  s/phy/PHY/ in subject and commit log
  s/pcie/PCIe/ in commit log

> @@ -912,7 +927,13 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
>  	 * The controller may have been left out of reset by the bootloader
>  	 * so make sure that we get a clean start by asserting resets here.
>  	 */
> -	reset_control_assert(pcie->phy_reset);
> +	reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> +				    pcie->phy_resets);
> +	usleep_range(5000, 10000);
> +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> +				  pcie->phy_resets);
> +	msleep(100);

Where did these usleep and msleep numbers come from?  They should use
a #define that we can connect back to a spec.

These delays should also be mentioned in the commit log because it
appears unrelated to the conversion to the reset_bulk API.  Actually,
it would be even better if they were in a separate patch, since it
looks like a logically separate change.

>  	reset_control_assert(pcie->mac_reset);
>  	usleep_range(10, 20);

Unrelated to this patch, but it would be nice to have an explanation
of this existing delay, too.

Bjorn
Lorenzo Bianconi June 21, 2024, 9:43 p.m. UTC | #2 
> On Fri, Jun 21, 2024 at 04:48:49PM +0200, Lorenzo Bianconi wrote:
> > Use reset_bulk APIs to manage phy reset lines. This is a preliminary
> > patch in order to add Airoha EN7581 pcie support.
> 
> If you have occasion to revise this:
> 
>   s/rely/Rely/ in subject
>   s/phy/PHY/ in subject and commit log
>   s/pcie/PCIe/ in commit log

ack, I will fix them in v2

> 
> > @@ -912,7 +927,13 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
> >  	 * The controller may have been left out of reset by the bootloader
> >  	 * so make sure that we get a clean start by asserting resets here.
> >  	 */
> > -	reset_control_assert(pcie->phy_reset);
> > +	reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> > +				    pcie->phy_resets);
> > +	usleep_range(5000, 10000);
> > +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> > +				  pcie->phy_resets);
> > +	msleep(100);
> 
> Where did these usleep and msleep numbers come from?  They should use
> a #define that we can connect back to a spec.

I think we can get rid of the first usleep_range() since we need to
deassert the line just to avoid unbalance in deassert_count counter since the
reset line is shared (the line is actually already de-assert). I will add a
comment to clarify it.

> 
> These delays should also be mentioned in the commit log because it
> appears unrelated to the conversion to the reset_bulk API.  Actually,
> it would be even better if they were in a separate patch, since it
> looks like a logically separate change.

Regarding the msleep(100), it is not documented in the vendor sdk, I think it
necessary to complete the reset before initialize the pcie-phy. Since it is
required just for EN7581, I guess we can move it in mtk_pcie_en7581_power_up()
(in patch 4/4) before the phy_init(). What do you think?

Regards,
Lorenzo

> 
> >  	reset_control_assert(pcie->mac_reset);
> >  	usleep_range(10, 20);
> 
> Unrelated to this patch, but it would be nice to have an explanation
> of this existing delay, too.
> 
> Bjorn
AngeloGioacchino Del Regno June 24, 2024, 8:01 a.m. UTC | #3 
Il 21/06/24 16:48, Lorenzo Bianconi ha scritto:
> Use reset_bulk APIs to manage phy reset lines. This is a preliminary
> patch in order to add Airoha EN7581 pcie support.
> 
> Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> ---
>   drivers/pci/controller/pcie-mediatek-gen3.c | 49 ++++++++++++++++-----
>   1 file changed, 37 insertions(+), 12 deletions(-)
> 
> diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> index 4859bd875bc4..9842617795a9 100644
> --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> @@ -100,14 +100,21 @@
>   #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
>   #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
>   
> +#define MAX_NUM_PHY_RSTS		1
> +
>   struct mtk_gen3_pcie;
>   
>   /**
>    * struct mtk_pcie_soc - differentiate between host generations
>    * @power_up: pcie power_up callback
> + * @phy_resets: phy reset lines SoC data.
>    */
>   struct mtk_pcie_soc {
>   	int (*power_up)(struct mtk_gen3_pcie *pcie);
> +	struct {
> +		const char *id[MAX_NUM_PHY_RSTS];
> +		int num_rsts;

Well, it's just two chars after all, so "num_resets" looks better imo.

> +	} phy_resets;
>   };
>   
>   /**
> @@ -128,7 +135,7 @@ struct mtk_msi_set {
>    * @base: IO mapped register base
>    * @reg_base: physical register base
>    * @mac_reset: MAC reset control
> - * @phy_reset: PHY reset control
> + * @phy_resets: PHY reset controllers
>    * @phy: PHY controller block
>    * @clks: PCIe clocks
>    * @num_clks: PCIe clocks count for this port
> @@ -148,7 +155,7 @@ struct mtk_gen3_pcie {
>   	void __iomem *base;
>   	phys_addr_t reg_base;
>   	struct reset_control *mac_reset;
> -	struct reset_control *phy_reset;
> +	struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RSTS];
>   	struct phy *phy;
>   	struct clk_bulk_data *clks;
>   	int num_clks;
> @@ -790,8 +797,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
>   {
>   	struct device *dev = pcie->dev;
>   	struct platform_device *pdev = to_platform_device(dev);
> +	int i, ret, num_rsts = pcie->soc->phy_resets.num_rsts; >   	struct resource *regs;
> -	int ret;
>   
>   	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
>   	if (!regs)
> @@ -804,12 +811,13 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
>   
>   	pcie->reg_base = regs->start;
>   
> -	pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
> -	if (IS_ERR(pcie->phy_reset)) {
> -		ret = PTR_ERR(pcie->phy_reset);
> -		if (ret != -EPROBE_DEFER)
> -			dev_err(dev, "failed to get PHY reset\n");
> +	for (i = 0; i < num_rsts; i++)
> +		pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
>   
> +	ret = devm_reset_control_bulk_get_optional_shared(dev, num_rsts,
> +							  pcie->phy_resets);

92 columns is ok, you can use one line for that.

> +	if (ret) {
> +		dev_err(dev, "failed to get PHY bulk reset\n");
>   		return ret;
>   	}
>   
> @@ -846,7 +854,12 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
>   	int err;
>   
>   	/* PHY power on and enable pipe clock */
> -	reset_control_deassert(pcie->phy_reset);
> +	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> +					  pcie->phy_resets);
> +	if (err) {
> +		dev_err(dev, "failed to deassert PHYs\n");
> +		return err;
> +	}
>   
>   	err = phy_init(pcie->phy);
>   	if (err) {
> @@ -882,7 +895,8 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
>   err_phy_on:
>   	phy_exit(pcie->phy);
>   err_phy_init:
> -	reset_control_assert(pcie->phy_reset);
> +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> +				  pcie->phy_resets);

same here

>   
>   	return err;
>   }
> @@ -897,7 +911,8 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
>   
>   	phy_power_off(pcie->phy);
>   	phy_exit(pcie->phy);
> -	reset_control_assert(pcie->phy_reset);
> +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> +				  pcie->phy_resets);

ditto

>   }
>   
>   static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
> @@ -912,7 +927,13 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
>   	 * The controller may have been left out of reset by the bootloader
>   	 * so make sure that we get a clean start by asserting resets here.
>   	 */
> -	reset_control_assert(pcie->phy_reset);
> +	reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> +				    pcie->phy_resets);

and again...

> +	usleep_range(5000, 10000);
> +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> +				  pcie->phy_resets);

.... :-)

Cheers,
Angelo

> +	msleep(100);
> +
>   	reset_control_assert(pcie->mac_reset);
>   	usleep_range(10, 20);
>   
> @@ -1090,6 +1111,10 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = {
>   
>   static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = {
>   	.power_up = mtk_pcie_power_up,
> +	.phy_resets = {
> +		.id[0] = "phy",
> +		.num_rsts = 1,
> +	},
>   };
>   
>   static const struct of_device_id mtk_pcie_of_match[] = {
Lorenzo Bianconi June 27, 2024, 7:03 a.m. UTC | #4 
> Il 21/06/24 16:48, Lorenzo Bianconi ha scritto:
> > Use reset_bulk APIs to manage phy reset lines. This is a preliminary
> > patch in order to add Airoha EN7581 pcie support.
> > 
> > Tested-by: Zhengping Zhang <zhengping.zhang@airoha.com>
> > Signed-off-by: Lorenzo Bianconi <lorenzo@kernel.org>
> > ---
> >   drivers/pci/controller/pcie-mediatek-gen3.c | 49 ++++++++++++++++-----
> >   1 file changed, 37 insertions(+), 12 deletions(-)
> > 
> > diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
> > index 4859bd875bc4..9842617795a9 100644
> > --- a/drivers/pci/controller/pcie-mediatek-gen3.c
> > +++ b/drivers/pci/controller/pcie-mediatek-gen3.c
> > @@ -100,14 +100,21 @@
> >   #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
> >   #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
> > +#define MAX_NUM_PHY_RSTS		1
> > +
> >   struct mtk_gen3_pcie;
> >   /**
> >    * struct mtk_pcie_soc - differentiate between host generations
> >    * @power_up: pcie power_up callback
> > + * @phy_resets: phy reset lines SoC data.
> >    */
> >   struct mtk_pcie_soc {
> >   	int (*power_up)(struct mtk_gen3_pcie *pcie);
> > +	struct {
> > +		const char *id[MAX_NUM_PHY_RSTS];
> > +		int num_rsts;
> 
> Well, it's just two chars after all, so "num_resets" looks better imo.

ack, fine. Naming is always hard :)

> 
> > +	} phy_resets;
> >   };
> >   /**
> > @@ -128,7 +135,7 @@ struct mtk_msi_set {
> >    * @base: IO mapped register base
> >    * @reg_base: physical register base
> >    * @mac_reset: MAC reset control
> > - * @phy_reset: PHY reset control
> > + * @phy_resets: PHY reset controllers
> >    * @phy: PHY controller block
> >    * @clks: PCIe clocks
> >    * @num_clks: PCIe clocks count for this port
> > @@ -148,7 +155,7 @@ struct mtk_gen3_pcie {
> >   	void __iomem *base;
> >   	phys_addr_t reg_base;
> >   	struct reset_control *mac_reset;
> > -	struct reset_control *phy_reset;
> > +	struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RSTS];
> >   	struct phy *phy;
> >   	struct clk_bulk_data *clks;
> >   	int num_clks;
> > @@ -790,8 +797,8 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
> >   {
> >   	struct device *dev = pcie->dev;
> >   	struct platform_device *pdev = to_platform_device(dev);
> > +	int i, ret, num_rsts = pcie->soc->phy_resets.num_rsts; >   	struct resource *regs;
> > -	int ret;
> >   	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
> >   	if (!regs)
> > @@ -804,12 +811,13 @@ static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
> >   	pcie->reg_base = regs->start;
> > -	pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
> > -	if (IS_ERR(pcie->phy_reset)) {
> > -		ret = PTR_ERR(pcie->phy_reset);
> > -		if (ret != -EPROBE_DEFER)
> > -			dev_err(dev, "failed to get PHY reset\n");
> > +	for (i = 0; i < num_rsts; i++)
> > +		pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
> > +	ret = devm_reset_control_bulk_get_optional_shared(dev, num_rsts,
> > +							  pcie->phy_resets);
> 
> 92 columns is ok, you can use one line for that.

I usually prefer to stay below 79 column limit, but I do not have a strong
opinion about it. I will fix it and even all below.

Regards,
Lorenzo

> 
> > +	if (ret) {
> > +		dev_err(dev, "failed to get PHY bulk reset\n");
> >   		return ret;
> >   	}
> > @@ -846,7 +854,12 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
> >   	int err;
> >   	/* PHY power on and enable pipe clock */
> > -	reset_control_deassert(pcie->phy_reset);
> > +	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> > +					  pcie->phy_resets);
> > +	if (err) {
> > +		dev_err(dev, "failed to deassert PHYs\n");
> > +		return err;
> > +	}
> >   	err = phy_init(pcie->phy);
> >   	if (err) {
> > @@ -882,7 +895,8 @@ static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
> >   err_phy_on:
> >   	phy_exit(pcie->phy);
> >   err_phy_init:
> > -	reset_control_assert(pcie->phy_reset);
> > +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> > +				  pcie->phy_resets);
> 
> same here
> 
> >   	return err;
> >   }
> > @@ -897,7 +911,8 @@ static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
> >   	phy_power_off(pcie->phy);
> >   	phy_exit(pcie->phy);
> > -	reset_control_assert(pcie->phy_reset);
> > +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> > +				  pcie->phy_resets);
> 
> ditto
> 
> >   }
> >   static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
> > @@ -912,7 +927,13 @@ static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
> >   	 * The controller may have been left out of reset by the bootloader
> >   	 * so make sure that we get a clean start by asserting resets here.
> >   	 */
> > -	reset_control_assert(pcie->phy_reset);
> > +	reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
> > +				    pcie->phy_resets);
> 
> and again...
> 
> > +	usleep_range(5000, 10000);
> > +	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
> > +				  pcie->phy_resets);
> 
> .... :-)
> 
> Cheers,
> Angelo
> 
> > +	msleep(100);
> > +
> >   	reset_control_assert(pcie->mac_reset);
> >   	usleep_range(10, 20);
> > @@ -1090,6 +1111,10 @@ static const struct dev_pm_ops mtk_pcie_pm_ops = {
> >   static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = {
> >   	.power_up = mtk_pcie_power_up,
> > +	.phy_resets = {
> > +		.id[0] = "phy",
> > +		.num_rsts = 1,
> > +	},
> >   };
> >   static const struct of_device_id mtk_pcie_of_match[] = {
>
diff mbox series

Patch

diff --git a/drivers/pci/controller/pcie-mediatek-gen3.c b/drivers/pci/controller/pcie-mediatek-gen3.c
index 4859bd875bc4..9842617795a9 100644
--- a/drivers/pci/controller/pcie-mediatek-gen3.c
+++ b/drivers/pci/controller/pcie-mediatek-gen3.c
@@ -100,14 +100,21 @@ 
 #define PCIE_ATR_TLP_TYPE_MEM		PCIE_ATR_TLP_TYPE(0)
 #define PCIE_ATR_TLP_TYPE_IO		PCIE_ATR_TLP_TYPE(2)
 
+#define MAX_NUM_PHY_RSTS		1
+
 struct mtk_gen3_pcie;
 
 /**
  * struct mtk_pcie_soc - differentiate between host generations
  * @power_up: pcie power_up callback
+ * @phy_resets: phy reset lines SoC data.
  */
 struct mtk_pcie_soc {
 	int (*power_up)(struct mtk_gen3_pcie *pcie);
+	struct {
+		const char *id[MAX_NUM_PHY_RSTS];
+		int num_rsts;
+	} phy_resets;
 };
 
 /**
@@ -128,7 +135,7 @@  struct mtk_msi_set {
  * @base: IO mapped register base
  * @reg_base: physical register base
  * @mac_reset: MAC reset control
- * @phy_reset: PHY reset control
+ * @phy_resets: PHY reset controllers
  * @phy: PHY controller block
  * @clks: PCIe clocks
  * @num_clks: PCIe clocks count for this port
@@ -148,7 +155,7 @@  struct mtk_gen3_pcie {
 	void __iomem *base;
 	phys_addr_t reg_base;
 	struct reset_control *mac_reset;
-	struct reset_control *phy_reset;
+	struct reset_control_bulk_data phy_resets[MAX_NUM_PHY_RSTS];
 	struct phy *phy;
 	struct clk_bulk_data *clks;
 	int num_clks;
@@ -790,8 +797,8 @@  static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
 {
 	struct device *dev = pcie->dev;
 	struct platform_device *pdev = to_platform_device(dev);
+	int i, ret, num_rsts = pcie->soc->phy_resets.num_rsts;
 	struct resource *regs;
-	int ret;
 
 	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");
 	if (!regs)
@@ -804,12 +811,13 @@  static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)
 
 	pcie->reg_base = regs->start;
 
-	pcie->phy_reset = devm_reset_control_get_optional_exclusive(dev, "phy");
-	if (IS_ERR(pcie->phy_reset)) {
-		ret = PTR_ERR(pcie->phy_reset);
-		if (ret != -EPROBE_DEFER)
-			dev_err(dev, "failed to get PHY reset\n");
+	for (i = 0; i < num_rsts; i++)
+		pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];
 
+	ret = devm_reset_control_bulk_get_optional_shared(dev, num_rsts,
+							  pcie->phy_resets);
+	if (ret) {
+		dev_err(dev, "failed to get PHY bulk reset\n");
 		return ret;
 	}
 
@@ -846,7 +854,12 @@  static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
 	int err;
 
 	/* PHY power on and enable pipe clock */
-	reset_control_deassert(pcie->phy_reset);
+	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
+					  pcie->phy_resets);
+	if (err) {
+		dev_err(dev, "failed to deassert PHYs\n");
+		return err;
+	}
 
 	err = phy_init(pcie->phy);
 	if (err) {
@@ -882,7 +895,8 @@  static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)
 err_phy_on:
 	phy_exit(pcie->phy);
 err_phy_init:
-	reset_control_assert(pcie->phy_reset);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
+				  pcie->phy_resets);
 
 	return err;
 }
@@ -897,7 +911,8 @@  static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)
 
 	phy_power_off(pcie->phy);
 	phy_exit(pcie->phy);
-	reset_control_assert(pcie->phy_reset);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
+				  pcie->phy_resets);
 }
 
 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
@@ -912,7 +927,13 @@  static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)
 	 * The controller may have been left out of reset by the bootloader
 	 * so make sure that we get a clean start by asserting resets here.
 	 */
-	reset_control_assert(pcie->phy_reset);
+	reset_control_bulk_deassert(pcie->soc->phy_resets.num_rsts,
+				    pcie->phy_resets);
+	usleep_range(5000, 10000);
+	reset_control_bulk_assert(pcie->soc->phy_resets.num_rsts,
+				  pcie->phy_resets);
+	msleep(100);
+
 	reset_control_assert(pcie->mac_reset);
 	usleep_range(10, 20);
 
@@ -1090,6 +1111,10 @@  static const struct dev_pm_ops mtk_pcie_pm_ops = {
 
 static const struct mtk_pcie_soc mtk_pcie_soc_mt8192 = {
 	.power_up = mtk_pcie_power_up,
+	.phy_resets = {
+		.id[0] = "phy",
+		.num_rsts = 1,
+	},
 };
 
 static const struct of_device_id mtk_pcie_of_match[] = {