| Message ID | 20240624-topic-sm8650-upstream-fix-dispcc-v2-1-ddaa13f3b207@linaro.org (mailing list archive) |
|---|---|
| State | Awaiting Upstream, archived |
| Headers | show |
| Series | clk: qcom: dispcc-sm8650: round of fixes | expand |
On Mon, Jun 24, 2024 at 10:05:50AM GMT, Neil Armstrong wrote: > The RCG's clk src has to be parked at XO while disabling as per the > HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. > > It also changes dptx1_aux_clk_src to use the correct ops instead of > clk_dp_ops. > > Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") > Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> > --- > drivers/clk/qcom/dispcc-sm8650.c | 14 +++++++------- > 1 file changed, 7 insertions(+), 7 deletions(-) > > diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c > index c9d2751f5cb8..360b80377ed6 100644 > --- a/drivers/clk/qcom/dispcc-sm8650.c > +++ b/drivers/clk/qcom/dispcc-sm8650.c > @@ -339,7 +339,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -398,7 +398,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_dp_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -457,7 +457,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -516,7 +516,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; The only parent for these three clocks is the DT_BI_TCXO. Is this really going to work as expected? Also what's the point of parking the TCXO-sourced clocks? > > @@ -560,7 +560,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { > .parent_data = disp_cc_parent_data_5, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -575,7 +575,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { > .parent_data = disp_cc_parent_data_5, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > @@ -647,7 +647,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { > .parent_data = disp_cc_parent_data_0, > .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), > .flags = CLK_SET_RATE_PARENT, > - .ops = &clk_rcg2_ops, > + .ops = &clk_rcg2_shared_ops, > }, > }; > > > -- > 2.34.1 >
On 24/06/2024 11:25, Dmitry Baryshkov wrote: > On Mon, Jun 24, 2024 at 10:05:50AM GMT, Neil Armstrong wrote: >> The RCG's clk src has to be parked at XO while disabling as per the >> HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. >> >> It also changes dptx1_aux_clk_src to use the correct ops instead of >> clk_dp_ops. >> >> Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") >> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> >> --- >> drivers/clk/qcom/dispcc-sm8650.c | 14 +++++++------- >> 1 file changed, 7 insertions(+), 7 deletions(-) >> >> diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c >> index c9d2751f5cb8..360b80377ed6 100644 >> --- a/drivers/clk/qcom/dispcc-sm8650.c >> +++ b/drivers/clk/qcom/dispcc-sm8650.c >> @@ -339,7 +339,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -398,7 +398,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_dp_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -457,7 +457,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -516,7 +516,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; > > The only parent for these three clocks is the DT_BI_TCXO. Is this really > going to work as expected? Also what's the point of parking the > TCXO-sourced clocks? > Indeed will drop Thanks, Neil >> >> @@ -560,7 +560,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { >> .parent_data = disp_cc_parent_data_5, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -575,7 +575,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { >> .parent_data = disp_cc_parent_data_5, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> @@ -647,7 +647,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { >> .parent_data = disp_cc_parent_data_0, >> .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), >> .flags = CLK_SET_RATE_PARENT, >> - .ops = &clk_rcg2_ops, >> + .ops = &clk_rcg2_shared_ops, >> }, >> }; >> >> >> -- >> 2.34.1 >> >
diff --git a/drivers/clk/qcom/dispcc-sm8650.c b/drivers/clk/qcom/dispcc-sm8650.c index c9d2751f5cb8..360b80377ed6 100644 --- a/drivers/clk/qcom/dispcc-sm8650.c +++ b/drivers/clk/qcom/dispcc-sm8650.c @@ -339,7 +339,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx0_aux_clk_src = { .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -398,7 +398,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx1_aux_clk_src = { .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_dp_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -457,7 +457,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx2_aux_clk_src = { .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -516,7 +516,7 @@ static struct clk_rcg2 disp_cc_mdss_dptx3_aux_clk_src = { .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -560,7 +560,7 @@ static struct clk_rcg2 disp_cc_mdss_esc0_clk_src = { .parent_data = disp_cc_parent_data_5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -575,7 +575,7 @@ static struct clk_rcg2 disp_cc_mdss_esc1_clk_src = { .parent_data = disp_cc_parent_data_5, .num_parents = ARRAY_SIZE(disp_cc_parent_data_5), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, }; @@ -647,7 +647,7 @@ static struct clk_rcg2 disp_cc_mdss_vsync_clk_src = { .parent_data = disp_cc_parent_data_0, .num_parents = ARRAY_SIZE(disp_cc_parent_data_0), .flags = CLK_SET_RATE_PARENT, - .ops = &clk_rcg2_ops, + .ops = &clk_rcg2_shared_ops, }, };
The RCG's clk src has to be parked at XO while disabling as per the HW recommendation, hence use clk_rcg2_shared_ops to achieve the same. It also changes dptx1_aux_clk_src to use the correct ops instead of clk_dp_ops. Fixes: 9e939f008338 ("clk: qcom: add the SM8650 Display Clock Controller driver") Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> --- drivers/clk/qcom/dispcc-sm8650.c | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-)