diff mbox series

[XEN,v2,04/13] x86/vpmu: address violations of MISRA C Rule 16.3

Message ID c45b27a08a1608de85e4bbae80763f8429d40ad5.1719218291.git.federico.serafini@bugseng.com (mailing list archive)
State Superseded
Headers show
Series x86: address some violations of MISRA C Rule 16.3 | expand

Commit Message

Federico Serafini June 24, 2024, 9:04 a.m. UTC
Add missing break statements to address violations of MISRA C Rule
16.3: "An unconditional `break' statement shall terminate every
switch-clause".

No functional change.

Signed-off-by: Federico Serafini <federico.serafini@bugseng.com>
---
 xen/arch/x86/cpu/vpmu.c       | 3 +++
 xen/arch/x86/cpu/vpmu_intel.c | 1 +
 2 files changed, 4 insertions(+)

Comments

Jan Beulich June 24, 2024, 3:16 p.m. UTC | #1
On 24.06.2024 11:04, Federico Serafini wrote:
> --- a/xen/arch/x86/cpu/vpmu_intel.c
> +++ b/xen/arch/x86/cpu/vpmu_intel.c
> @@ -713,6 +713,7 @@ static int cf_check core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
>              break;
>          default:
>              rdmsrl(msr, *msr_content);
> +            break;
>          }
>      }
>      else if ( msr == MSR_IA32_MISC_ENABLE )

Up from here, in core2_vpmu_do_wrmsr() there's a pretty long default
block with no terminating break. Is there a reason that you don't put
one there?

Jan
Stefano Stabellini June 25, 2024, 12:52 a.m. UTC | #2
On Mon, 24 Jun 2024, Federico Serafini wrote:
> Add missing break statements to address violations of MISRA C Rule
> 16.3: "An unconditional `break' statement shall terminate every
> switch-clause".
> 
> No functional change.
> 
> Signed-off-by: Federico Serafini <federico.serafini@bugseng.com>

Reviewed-by: Stefano Stabellini <sstabellini@kernel.org>
Federico Serafini June 25, 2024, 9:53 a.m. UTC | #3
On 24/06/24 17:16, Jan Beulich wrote:
> On 24.06.2024 11:04, Federico Serafini wrote:
>> --- a/xen/arch/x86/cpu/vpmu_intel.c
>> +++ b/xen/arch/x86/cpu/vpmu_intel.c
>> @@ -713,6 +713,7 @@ static int cf_check core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
>>               break;
>>           default:
>>               rdmsrl(msr, *msr_content);
>> +            break;
>>           }
>>       }
>>       else if ( msr == MSR_IA32_MISC_ENABLE )
> 
> Up from here, in core2_vpmu_do_wrmsr() there's a pretty long default
> block with no terminating break. Is there a reason that you don't put
> one there?

I noticed that vpmu_intel.c is a file out-of-scope.
The violation I addressed was shown because it involves
the macro rdmsrl coming from file xen/arch/x86/include/asm/msr.h
(in scope).
I will address also the violation you pointed out in a v3.
diff mbox series

Patch

diff --git a/xen/arch/x86/cpu/vpmu.c b/xen/arch/x86/cpu/vpmu.c
index a7bc0cd1fc..b2ba999412 100644
--- a/xen/arch/x86/cpu/vpmu.c
+++ b/xen/arch/x86/cpu/vpmu.c
@@ -663,6 +663,8 @@  long do_xenpmu_op(
 
         if ( pmu_params.version.maj != XENPMU_VER_MAJ )
             return -EINVAL;
+
+        break;
     }
 
     switch ( op )
@@ -776,6 +778,7 @@  long do_xenpmu_op(
 
     default:
         ret = -EINVAL;
+        break;
     }
 
     return ret;
diff --git a/xen/arch/x86/cpu/vpmu_intel.c b/xen/arch/x86/cpu/vpmu_intel.c
index cd414165df..46f3ff86e7 100644
--- a/xen/arch/x86/cpu/vpmu_intel.c
+++ b/xen/arch/x86/cpu/vpmu_intel.c
@@ -713,6 +713,7 @@  static int cf_check core2_vpmu_do_rdmsr(unsigned int msr, uint64_t *msr_content)
             break;
         default:
             rdmsrl(msr, *msr_content);
+            break;
         }
     }
     else if ( msr == MSR_IA32_MISC_ENABLE )