diff mbox series

arm64: dts: rockchip: Delete the SoC variant dtsi for RK3399Pro

Message ID 4449f7d4eead787308300e2d1d37b88c9d1446b2.1717308862.git.dsimic@manjaro.org (mailing list archive)
State New
Headers show
Series arm64: dts: rockchip: Delete the SoC variant dtsi for RK3399Pro | expand

Commit Message

Dragan Simic June 2, 2024, 6:25 a.m. UTC 
The commit 587b4ee24fc7 ("arm64: dts: rockchip: add core dtsi file for
RK3399Pro SoCs") describes the RK3399Pro's PCI Express interface as the way
built-in NPU communicates with the rest of the SoC.  All available evidence
shows this not to be accurate, as described in detail below.  Moreover, the
rk3399pro.dtsi isn't used anywhere, so let's delete it.

The publicly available schematics of the Radxa Rock Pi N10 carrier board [1]
and the Vamrs VMARC RK3399Pro SoM, [2] which put together form the currently
single supported RK3399Pro-based board, clearly show that the PCI Express x4
interface of this SoC is fully functional and actually not used by the SoC
to communicate with the built-in NPU.  In more detail, the VMARC SoM exports
the SoC's PCI Express interface at its board-to-board connector, and the Rock
Pi N10 routes it to an M.2 M-key slot with four PCI Express lanes.

Both the Rockchip RK3399Pro datasheet, version 1.1, [3] and the Rockchip
RK3399Pro technical reference manual (TRM), first part of the version 1.0, [4]
don't describe that the SoC's PCI Express interface is reserved for the NPU.
Instead, the RK3399Pro TRM describes that the NPU uses AHB and AXI interfaces
as the host interface (HIF).  The RK3399Pro datasheet clearly describes that
the PCI Express x4 interface is available for general-purpose use, just like
it's the case with the standard Rockchip RK3399 SoC, [5] albeit with a bit
shorter feature list provided in the RK3399Pro datasheet.

Even the publicly available reference RK3399Pro schematic from Rockchip [6]
shows the availability of a standard PCI Express slot with four lanes, which
would be pretty much impossible if the PCI Express interface was reserved
for the communication with the built-in NPU.

Based on the RK3399Pro datasheet [3] and the board schematics, [2][6] the
built-in NPU actually exports NPU_PCIE as a separate PCI Express x2 interface
that's partially pinmuxed with the NPU's separate USB 3.0 interface, which is
described further in the next paragraph.  However, the NPU's separate PCI
Express x2 interface is left undocumented in the publicly available RK3399Pro
documentation, in which it's clearly described as reserved for internal use
and not intended for the communication with the NPU.  Finally, the evidently
independent nature of the separate NPU_PCIE x2 interface makes ignoring it
safe when it comes to determining the nature and the availability of the
RK3399Pro's main PCI Express x4 interface.

The actual application-level communication with the built-in NPU, including
powering it up and down and uploading the NPU firmware, is performed through
the separate USB 2.0 and USB 3.0 interfaces exported by the NPU, [7] which
the VMARC SoM [2] and the reference board design from Rockchip [6] route to
the SoC's standard USB 2.0 and USB 3.0 interfaces, to make the NPU accessible
to software running on the SoC's ARM cores.

[1] https://dl.radxa.com/rockpin10/docs/hw/rockpi_n10_sch_v1.1_20190909.pdf
[2] https://dl.radxa.com/rockpin10/docs/hw/VMARC_RK3399Pro_sch_V1.1_20190619.pdf
[3] https://www.rockchip.fr/RK3399Pro%20datasheet%20V1.1.pdf
[4] https://www.rockchip.fr/Rockchip%20RK3399Pro%20TRM%20V1.0%20Part1.pdf
[5] https://www.rockchip.fr/RK3399%20datasheet%20V1.8.pdf
[6] https://opensource.rock-chips.com/images/e/e4/RK_EVB_RK3399PRO_LP3S178P332SD8_V11_20181113_RZF.pdf
[7] https://wiki.radxa.com/RockpiN10/dev/NPU-booting

Signed-off-by: Dragan Simic <dsimic@manjaro.org>
---
 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 ---------------------
 1 file changed, 22 deletions(-)
 delete mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi

Comments

Dragan Simic June 24, 2024, 5:55 p.m. UTC | #1 
Hello all,

Just checking, are there any comments on this patch?  Is there something
more I can do to have it accepted?


On 2024-06-02 08:25, Dragan Simic wrote:
> The commit 587b4ee24fc7 ("arm64: dts: rockchip: add core dtsi file for
> RK3399Pro SoCs") describes the RK3399Pro's PCI Express interface as the 
> way
> built-in NPU communicates with the rest of the SoC.  All available 
> evidence
> shows this not to be accurate, as described in detail below.  Moreover, 
> the
> rk3399pro.dtsi isn't used anywhere, so let's delete it.
> 
> The publicly available schematics of the Radxa Rock Pi N10 carrier 
> board [1]
> and the Vamrs VMARC RK3399Pro SoM, [2] which put together form the 
> currently
> single supported RK3399Pro-based board, clearly show that the PCI 
> Express x4
> interface of this SoC is fully functional and actually not used by the 
> SoC
> to communicate with the built-in NPU.  In more detail, the VMARC SoM 
> exports
> the SoC's PCI Express interface at its board-to-board connector, and 
> the Rock
> Pi N10 routes it to an M.2 M-key slot with four PCI Express lanes.
> 
> Both the Rockchip RK3399Pro datasheet, version 1.1, [3] and the 
> Rockchip
> RK3399Pro technical reference manual (TRM), first part of the version 
> 1.0, [4]
> don't describe that the SoC's PCI Express interface is reserved for the 
> NPU.
> Instead, the RK3399Pro TRM describes that the NPU uses AHB and AXI 
> interfaces
> as the host interface (HIF).  The RK3399Pro datasheet clearly describes 
> that
> the PCI Express x4 interface is available for general-purpose use, just 
> like
> it's the case with the standard Rockchip RK3399 SoC, [5] albeit with a 
> bit
> shorter feature list provided in the RK3399Pro datasheet.
> 
> Even the publicly available reference RK3399Pro schematic from Rockchip 
> [6]
> shows the availability of a standard PCI Express slot with four lanes, 
> which
> would be pretty much impossible if the PCI Express interface was 
> reserved
> for the communication with the built-in NPU.
> 
> Based on the RK3399Pro datasheet [3] and the board schematics, [2][6] 
> the
> built-in NPU actually exports NPU_PCIE as a separate PCI Express x2 
> interface
> that's partially pinmuxed with the NPU's separate USB 3.0 interface, 
> which is
> described further in the next paragraph.  However, the NPU's separate 
> PCI
> Express x2 interface is left undocumented in the publicly available 
> RK3399Pro
> documentation, in which it's clearly described as reserved for internal 
> use
> and not intended for the communication with the NPU.  Finally, the 
> evidently
> independent nature of the separate NPU_PCIE x2 interface makes ignoring 
> it
> safe when it comes to determining the nature and the availability of 
> the
> RK3399Pro's main PCI Express x4 interface.
> 
> The actual application-level communication with the built-in NPU, 
> including
> powering it up and down and uploading the NPU firmware, is performed 
> through
> the separate USB 2.0 and USB 3.0 interfaces exported by the NPU, [7] 
> which
> the VMARC SoM [2] and the reference board design from Rockchip [6] 
> route to
> the SoC's standard USB 2.0 and USB 3.0 interfaces, to make the NPU 
> accessible
> to software running on the SoC's ARM cores.
> 
> [1] 
> https://dl.radxa.com/rockpin10/docs/hw/rockpi_n10_sch_v1.1_20190909.pdf
> [2] 
> https://dl.radxa.com/rockpin10/docs/hw/VMARC_RK3399Pro_sch_V1.1_20190619.pdf
> [3] https://www.rockchip.fr/RK3399Pro%20datasheet%20V1.1.pdf
> [4] 
> https://www.rockchip.fr/Rockchip%20RK3399Pro%20TRM%20V1.0%20Part1.pdf
> [5] https://www.rockchip.fr/RK3399%20datasheet%20V1.8.pdf
> [6] 
> https://opensource.rock-chips.com/images/e/e4/RK_EVB_RK3399PRO_LP3S178P332SD8_V11_20181113_RZF.pdf
> [7] https://wiki.radxa.com/RockpiN10/dev/NPU-booting
> 
> Signed-off-by: Dragan Simic <dsimic@manjaro.org>
> ---
>  arch/arm64/boot/dts/rockchip/rk3399pro.dtsi | 22 ---------------------
>  1 file changed, 22 deletions(-)
>  delete mode 100644 arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> 
> diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> deleted file mode 100644
> index bb5ebf6608b9..000000000000
> --- a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
> +++ /dev/null
> @@ -1,22 +0,0 @@
> -// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> -// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
> -
> -#include "rk3399.dtsi"
> -
> -/ {
> -	compatible = "rockchip,rk3399pro";
> -};
> -
> -/* Default to enabled since AP talk to NPU part over pcie */
> -&pcie_phy {
> -	status = "okay";
> -};
> -
> -/* Default to enabled since AP talk to NPU part over pcie */
> -&pcie0 {
> -	ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
> -	num-lanes = <4>;
> -	pinctrl-names = "default";
> -	pinctrl-0 = <&pcie_clkreqn_cpm>;
> -	status = "okay";
> -};
> 
> _______________________________________________
> Linux-rockchip mailing list
> Linux-rockchip@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-rockchip
Alexey Charkov June 24, 2024, 5:59 p.m. UTC | #2 
On Mon, Jun 24, 2024 at 9:55 PM Dragan Simic <dsimic@manjaro.org> wrote:
>
> Hello all,
>
> Just checking, are there any comments on this patch?  Is there something
> more I can do to have it accepted?

Hi Dragan,

Heiko has already applied it quietly a couple of days ago [1], and
also merged the v5 thermal and OPP code that I rebased on top of this
patch of yours.

Thanks a lot Heiko and Dragan!

Best regards,
Alexey

[1] https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=for-next&id=def88eb4d8365a4aa064d28405d03550a9d0a3be
Alexey Charkov June 24, 2024, 6:03 p.m. UTC | #3 
On Mon, Jun 24, 2024 at 9:59 PM Alexey Charkov <alchark@gmail.com> wrote:
>
> On Mon, Jun 24, 2024 at 9:55 PM Dragan Simic <dsimic@manjaro.org> wrote:
> >
> > Hello all,
> >
> > Just checking, are there any comments on this patch?  Is there something
> > more I can do to have it accepted?
>
> Hi Dragan,
>
> Heiko has already applied it quietly a couple of days ago [1], and
> also merged the v5 thermal and OPP code that I rebased on top of this
> patch of yours.

Oops, that was about a different patch, sorry. But still thanks a lot
to Heiko and Dragan :)

Best regards,
Alexey
Dragan Simic June 24, 2024, 6:06 p.m. UTC | #4 
Hello Alexey,

On 2024-06-24 19:59, Alexey Charkov wrote:
> On Mon, Jun 24, 2024 at 9:55 PM Dragan Simic <dsimic@manjaro.org> 
> wrote:
>> Just checking, are there any comments on this patch?  Is there 
>> something
>> more I can do to have it accepted?
> 
> Heiko has already applied it quietly a couple of days ago [1], and
> also merged the v5 thermal and OPP code that I rebased on top of this
> patch of yours.

Yes, I saw that already, but this patch is a different one, it's about
deleting the redundant .dtsi for RK3399Pro. :)

Regarding your v5, I've had some health issues, so I unfortunately 
haven't
managed to review it and test in detail yet.  I'll do that as soon as 
possible,
and I'll come back with any comments I might have.

> [1] 
> https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git/commit/?h=for-next&id=def88eb4d8365a4aa064d28405d03550a9d0a3be
Heiko Stuebner June 24, 2024, 7:40 p.m. UTC | #5 
Am Montag, 24. Juni 2024, 20:06:19 CEST schrieb Dragan Simic:
> Hello Alexey,
> 
> On 2024-06-24 19:59, Alexey Charkov wrote:
> > On Mon, Jun 24, 2024 at 9:55 PM Dragan Simic <dsimic@manjaro.org> 
> > wrote:
> >> Just checking, are there any comments on this patch?  Is there 
> >> something
> >> more I can do to have it accepted?
> > 
> > Heiko has already applied it quietly a couple of days ago [1], and
> > also merged the v5 thermal and OPP code that I rebased on top of this
> > patch of yours.
> 
> Yes, I saw that already, but this patch is a different one, it's about
> deleting the redundant .dtsi for RK3399Pro. :)

thanks for the reminder, somehow I overlooked this one in my patchrun
today.

> Regarding your v5, I've had some health issues, so I unfortunately 
> haven't
> managed to review it and test in detail yet.  I'll do that as soon as 
> possible,
> and I'll come back with any comments I might have.

if you have comments, please send follow-up patches :-)
Heiko Stuebner June 27, 2024, 7:27 p.m. UTC | #6 
On Sun, 2 Jun 2024 08:25:38 +0200, Dragan Simic wrote:
> The commit 587b4ee24fc7 ("arm64: dts: rockchip: add core dtsi file for
> RK3399Pro SoCs") describes the RK3399Pro's PCI Express interface as the way
> built-in NPU communicates with the rest of the SoC.  All available evidence
> shows this not to be accurate, as described in detail below.  Moreover, the
> rk3399pro.dtsi isn't used anywhere, so let's delete it.
> 
> The publicly available schematics of the Radxa Rock Pi N10 carrier board [1]
> and the Vamrs VMARC RK3399Pro SoM, [2] which put together form the currently
> single supported RK3399Pro-based board, clearly show that the PCI Express x4
> interface of this SoC is fully functional and actually not used by the SoC
> to communicate with the built-in NPU.  In more detail, the VMARC SoM exports
> the SoC's PCI Express interface at its board-to-board connector, and the Rock
> Pi N10 routes it to an M.2 M-key slot with four PCI Express lanes.
> 
> [...]

Applied, thanks!

[1/1] arm64: dts: rockchip: Delete the SoC variant dtsi for RK3399Pro
      commit: 40113edfe63310ad529700fca24f2ebd49ae09ea

Best regards,
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi b/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
deleted file mode 100644
index bb5ebf6608b9..000000000000
--- a/arch/arm64/boot/dts/rockchip/rk3399pro.dtsi
+++ /dev/null
@@ -1,22 +0,0 @@ 
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-// Copyright (c) 2019 Fuzhou Rockchip Electronics Co., Ltd.
-
-#include "rk3399.dtsi"
-
-/ {
-	compatible = "rockchip,rk3399pro";
-};
-
-/* Default to enabled since AP talk to NPU part over pcie */
-&pcie_phy {
-	status = "okay";
-};
-
-/* Default to enabled since AP talk to NPU part over pcie */
-&pcie0 {
-	ep-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
-	num-lanes = <4>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_clkreqn_cpm>;
-	status = "okay";
-};