| Message ID | 20240615021507.122035-3-kanakshilledar@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 1f6e218859f1833d8fa4054bf76fd59da743cb22 |
| Headers | show |
| Series | dt-bindings: interrupt-controller: riscv,cpu-intc | expand |
On Sat, 15 Jun 2024 07:45:04 +0530, Kanak Shilledar wrote: > removed the redundant properties for interrupt-controller > and provide reference to the riscv,cpu-intc.yaml which defines > the interrupt-controller. making the properties for riscv > interrupt-controller at a central place. > > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Kanak Shilledar <kanakshilledar@gmail.com> > --- > Changes in v4: > - Change DCO email to @gmail.com > Changes in v3: > - No change. > - Rolling out as RESEND. > Changes in v2: > - Fix warning of `type` is a required property during `make > dt_bindings_check`. > --- > .../devicetree/bindings/riscv/cpus.yaml | 21 +------------------ > 1 file changed, 1 insertion(+), 20 deletions(-) > Applied, thanks!
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b..f1241e5e8753 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -102,26 +102,7 @@ properties: interrupt-controller: type: object - additionalProperties: false - description: Describes the CPU's local interrupt controller - - properties: - '#interrupt-cells': - const: 1 - - compatible: - oneOf: - - items: - - const: andestech,cpu-intc - - const: riscv,cpu-intc - - const: riscv,cpu-intc - - interrupt-controller: true - - required: - - '#interrupt-cells' - - compatible - - interrupt-controller + $ref: /schemas/interrupt-controller/riscv,cpu-intc.yaml# cpu-idle-states: $ref: /schemas/types.yaml#/definitions/phandle-array