| Message ID | 20240610233221.242749-5-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive) |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add CPG support for RZ/V2H(P) SoC | expand |
On Tue, Jun 11, 2024 at 1:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > Add RZ/V2H(P) CPG driver. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > --- > v1->v2 > - Updated commit description > - Dropped pll_clk1/clk2_offset > - Made r9a09g057_mod_clks/r9a09g057_resets as static const > - Now using register indexes Thanks for the update! > --- /dev/null > +++ b/drivers/clk/renesas/r9a09g057-cpg.c > +static const struct rzv2h_mod_clk r9a09g057_mod_clks[] = { > + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), So this relates to module clock 8 * 16 + 15 = 143 in DTS... > +}; > + > +static const struct rzv2h_reset r9a09g057_resets[] = { > + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ > +}; > + > +static const unsigned int r9a09g057_crit_mod_clks[] __initconst = { > + MOD_CLK_BASE + 5, /* ICU_0_PCLK_I */ > + MOD_CLK_BASE + 19, /* GIC_0_GICCLK */ So these relate to module clocks 5 and 19 in DTS. Actually none of these clocks are created in the driver yet, so I think these critical clocks belong to the patch that will introduce them. I am wondering if critical clocks should just use a flag in DEF_MOD() instead... The rest LGTM. Gr{oetje,eeting}s, Geert
Hi Geert, Thank you for the review. On Wed, Jun 26, 2024 at 11:14 AM Geert Uytterhoeven <geert@linux-m68k.org> wrote: > > On Tue, Jun 11, 2024 at 1:32 AM Prabhakar <prabhakar.csengg@gmail.com> wrote: > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > > > Add RZ/V2H(P) CPG driver. > > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> > > --- > > v1->v2 > > - Updated commit description > > - Dropped pll_clk1/clk2_offset > > - Made r9a09g057_mod_clks/r9a09g057_resets as static const > > - Now using register indexes > > Thanks for the update! > > > --- /dev/null > > +++ b/drivers/clk/renesas/r9a09g057-cpg.c > > > +static const struct rzv2h_mod_clk r9a09g057_mod_clks[] = { > > + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), > > So this relates to module clock 8 * 16 + 15 = 143 in DTS... > Yep. > > +}; > > + > > +static const struct rzv2h_reset r9a09g057_resets[] = { > > + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ > > +}; > > + > > +static const unsigned int r9a09g057_crit_mod_clks[] __initconst = { > > + MOD_CLK_BASE + 5, /* ICU_0_PCLK_I */ > > + MOD_CLK_BASE + 19, /* GIC_0_GICCLK */ > > So these relate to module clocks 5 and 19 in DTS. > > Actually none of these clocks are created in the driver yet, so I think > these critical clocks belong to the patch that will introduce them. > > I am wondering if critical clocks should just use a flag in DEF_MOD() > instead... > Agreed, I will add a flag for it and have two macros like below, #define DEF_MOD_BASE(_name, _parent, _id, _critical, _onindex, _onbit, _monindex, _monbit) \ { \ .name = (_name), \ .parent = (_parent), \ .id = (_id), \ .critical = (_critical), \ .on_index = (_onindex), \ .on_bit = (_onbit), \ .mon_index = (_monindex), \ .mon_bit = (_monbit), \ } #define MOD_CLK_ID(x) (MOD_CLK_BASE + (x)) #define MOD_ID(x, y) ((((x) * 16)) + (y)) #define DEF_MOD(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ DEF_MOD_BASE(_name, _parent, MOD_CLK_ID(MOD_ID(_onindex, _onbit)), \ false, _onindex, _onbit, _monindex, _monbit) #define DEF_MOD_CRITICAL(_name, _parent, _onindex, _onbit, _monindex, _monbit) \ DEF_MOD_BASE(_name, _parent, MOD_CLK_ID(MOD_ID(_onindex, _onbit)), \ true, _onindex, _onbit, _monindex, _monbit) Cheers, Prabhakar
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig index 330c8bc03777..3f3f84eb357b 100644 --- a/drivers/clk/renesas/Kconfig +++ b/drivers/clk/renesas/Kconfig @@ -40,6 +40,7 @@ config CLK_RENESAS select CLK_R9A07G054 if ARCH_R9A07G054 select CLK_R9A08G045 if ARCH_R9A08G045 select CLK_R9A09G011 if ARCH_R9A09G011 + select CLK_R9A09G057 if ARCH_R9A09G057 select CLK_SH73A0 if ARCH_SH73A0 if CLK_RENESAS @@ -193,6 +194,10 @@ config CLK_R9A09G011 bool "RZ/V2M clock support" if COMPILE_TEST select CLK_RZG2L +config CLK_R9A09G057 + bool "RZ/V2H(P) clock support" if COMPILE_TEST + select CLK_RZV2H + config CLK_SH73A0 bool "SH-Mobile AG5 clock support" if COMPILE_TEST select CLK_RENESAS_CPG_MSTP diff --git a/drivers/clk/renesas/Makefile b/drivers/clk/renesas/Makefile index d81a62e78345..23d2e26051c8 100644 --- a/drivers/clk/renesas/Makefile +++ b/drivers/clk/renesas/Makefile @@ -37,6 +37,7 @@ obj-$(CONFIG_CLK_R9A07G044) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A07G054) += r9a07g044-cpg.o obj-$(CONFIG_CLK_R9A08G045) += r9a08g045-cpg.o obj-$(CONFIG_CLK_R9A09G011) += r9a09g011-cpg.o +obj-$(CONFIG_CLK_R9A09G057) += r9a09g057-cpg.o obj-$(CONFIG_CLK_SH73A0) += clk-sh73a0.o # Family diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a09g057-cpg.c new file mode 100644 index 000000000000..d47b4365b2de --- /dev/null +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Renesas RZ/V2H(P) CPG driver + * + * Copyright (C) 2024 Renesas Electronics Corp. + */ + +#include <linux/clk-provider.h> +#include <linux/device.h> +#include <linux/init.h> +#include <linux/kernel.h> + +#include <dt-bindings/clock/r9a09g057-cpg.h> + +#include "rzv2h-cpg.h" + +enum clk_ids { + /* Core Clock Outputs exported to DT */ + LAST_DT_CORE_CLK = R9A09G057_IOTOP_0_SHCLK, + + /* External Input Clocks */ + CLK_QEXTAL, + + /* Internal Core Clocks */ + CLK_PLLCM33, + CLK_PLLCM33_DIV16, + CLK_PLLCA55, + + /* Module Clocks */ + MOD_CLK_BASE, +}; + +static const struct cpg_core_clk r9a09g057_core_clks[] __initconst = { + /* External Clock Inputs */ + DEF_INPUT("qextal", CLK_QEXTAL), + + /* Internal Core Clocks */ + DEF_FIXED(".pllcm33", CLK_PLLCM33, CLK_QEXTAL, 200, 3), + DEF_FIXED(".pllcm33_div16", CLK_PLLCM33_DIV16, CLK_PLLCM33, 1, 16), + + DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLL_CONF(0x64)), +}; + +static const struct rzv2h_mod_clk r9a09g057_mod_clks[] = { + DEF_MOD("scif_0_clk_pck", CLK_PLLCM33_DIV16, 8, 15, 4, 15), +}; + +static const struct rzv2h_reset r9a09g057_resets[] = { + DEF_RST(9, 5, 4, 6), /* SCIF_0_RST_SYSTEM_N */ +}; + +static const unsigned int r9a09g057_crit_mod_clks[] __initconst = { + MOD_CLK_BASE + 5, /* ICU_0_PCLK_I */ + MOD_CLK_BASE + 19, /* GIC_0_GICCLK */ +}; + +const struct rzv2h_cpg_info r9a09g057_cpg_info = { + /* Core Clocks */ + .core_clks = r9a09g057_core_clks, + .num_core_clks = ARRAY_SIZE(r9a09g057_core_clks), + .last_dt_core_clk = LAST_DT_CORE_CLK, + .num_total_core_clks = MOD_CLK_BASE, + + /* Critical Module Clocks */ + .crit_mod_clks = r9a09g057_crit_mod_clks, + .num_crit_mod_clks = ARRAY_SIZE(r9a09g057_crit_mod_clks), + + /* Module Clocks */ + .mod_clks = r9a09g057_mod_clks, + .num_mod_clks = ARRAY_SIZE(r9a09g057_mod_clks), + .num_hw_mod_clks = 25 * 16, + + /* Resets */ + .resets = r9a09g057_resets, + .num_resets = ARRAY_SIZE(r9a09g057_resets), + .num_hw_resets = 18 * 16, +}; diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cpg.c index f3c9f562234b..7882cfb36998 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -652,6 +652,10 @@ static int __init rzv2h_cpg_probe(struct platform_device *pdev) } static const struct of_device_id rzv2h_cpg_match[] = { + { + .compatible = "renesas,r9a09g057-cpg", + .data = &r9a09g057_cpg_info, + }, { /* sentinel */ } }; diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cpg.h index d2791a3a23a0..2a4411618b8a 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -159,4 +159,6 @@ struct rzv2h_cpg_info { unsigned int num_crit_mod_clks; }; +extern const struct rzv2h_cpg_info r9a09g057_cpg_info; + #endif /* __RENESAS_RZV2H_CPG_H__ */