| Message ID | 20240617091418.2956380-1-etienne.carriere@foss.st.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | ARM: dts: stm32: OP-TEE async notif interrupt for ST STM32MP15x boards | expand |
Hi Etienne On 6/17/24 11:14, Etienne Carriere wrote: > Define the GIC interrupt (PPI 15) to be used on ST STM32MP15x boards > for OP-TEE async notif. > > Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> > --- > arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 5 +++++ > arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 +++++ > arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 5 +++++ > arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 +++++ > 4 files changed, 20 insertions(+) > > diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts > index 306e1bc2a514..847b360f02fc 100644 > --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts > +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts > @@ -62,6 +62,11 @@ &m4_rproc { > reset-names = "mcu_rst", "hold_boot"; ... Applied on stm32-next. Thanks!! Alex
diff --git a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts index 306e1bc2a514..847b360f02fc 100644 --- a/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts @@ -62,6 +62,11 @@ &m4_rproc { reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts index 956da5f26c1c..43280289759d 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts @@ -68,6 +68,11 @@ &m4_rproc { reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts index 8e4b0db198c2..6f27d794d270 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts @@ -67,6 +67,11 @@ &m4_rproc { reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi"; diff --git a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts index 72b9cab2d990..6ae391bffee5 100644 --- a/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts +++ b/arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts @@ -72,6 +72,11 @@ &m4_rproc { reset-names = "mcu_rst", "hold_boot"; }; +&optee { + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 15 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>; +}; + &rcc { compatible = "st,stm32mp1-rcc-secure", "syscon"; clock-names = "hse", "hsi", "csi", "lse", "lsi";
Define the GIC interrupt (PPI 15) to be used on ST STM32MP15x boards for OP-TEE async notif. Signed-off-by: Etienne Carriere <etienne.carriere@foss.st.com> --- arch/arm/boot/dts/st/stm32mp157a-dk1-scmi.dts | 5 +++++ arch/arm/boot/dts/st/stm32mp157c-dk2-scmi.dts | 5 +++++ arch/arm/boot/dts/st/stm32mp157c-ed1-scmi.dts | 5 +++++ arch/arm/boot/dts/st/stm32mp157c-ev1-scmi.dts | 5 +++++ 4 files changed, 20 insertions(+)