| Message ID | 20240627123911.227480-3-o.rempel@pengutronix.de (mailing list archive) |
|---|---|
| State | Changes Requested |
| Delegated to: | Netdev Maintainers |
| Headers | show |
| Series | [net-next,v1,1/1] net: dsa: microchip: add regmap_range for KSZ9563 chip | expand |
| Context | Check | Description |
|---|---|---|
| netdev/tree_selection | success | Clearly marked for net-next |
| netdev/apply | fail | Patch does not apply to net-next-1 |
On Thu, Jun 27, 2024 at 02:39:10PM +0200, Oleksij Rempel wrote: > From: Lucas Stach <l.stach@pengutronix.de> > > The register manual and datasheet documentation for the LAN937x series > disagree about the polarity of the MII mode strap. As a consequence > there are hardware designs that have the RGMII interface strapped into > MAC mode, which is a invalid configuration and will prevent the internal > clock from being fed into the port TX interface. What i think is missing from this is that you are talking about the CPU port. For a normal user point, RGMII MAC mode would make sense, if there is an external RGMII PHY attached. And the code only does this if the port is a CPU port. So maybe: ... that have the CPU port RGMII interface ... Andrew
On Thu, Jun 27, 2024 at 02:39:10PM +0200, Oleksij Rempel wrote: > From: Lucas Stach <l.stach@pengutronix.de> > > The register manual and datasheet documentation for the LAN937x series > disagree about the polarity of the MII mode strap. As a consequence > there are hardware designs that have the RGMII interface strapped into > MAC mode, which is a invalid configuration and will prevent the internal > clock from being fed into the port TX interface. > > Force the MII mode to PHY for RGMII interfaces where this is the only > valid mode, to override the inproper strapping. > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> > --- What's the difference between MAC mode and PHY mode with RGMII for this switch?
On Fri, Jun 28, 2024 at 01:25:43AM +0300, Vladimir Oltean wrote: > On Thu, Jun 27, 2024 at 02:39:10PM +0200, Oleksij Rempel wrote: > > From: Lucas Stach <l.stach@pengutronix.de> > > > > The register manual and datasheet documentation for the LAN937x series > > disagree about the polarity of the MII mode strap. As a consequence > > there are hardware designs that have the RGMII interface strapped into > > MAC mode, which is a invalid configuration and will prevent the internal > > clock from being fed into the port TX interface. > > > > Force the MII mode to PHY for RGMII interfaces where this is the only > > valid mode, to override the inproper strapping. > > > > Signed-off-by: Lucas Stach <l.stach@pengutronix.de> > > Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> > > --- > > What's the difference between MAC mode and PHY mode with RGMII for this switch? Let's take a step back. I'll describe first my initial findings, the symptoms, and my new findings from today, so my argumentation and the patch itself should be updated. Initially, we identified that the RGMIIx_MODE[1,0] strap pins select between RGMII, RMII, and MII. The MIIx_PHY_MODE pin configures PHY mode for MII or clock direction in RMII but should have no effect in RGMII mode. However, if MIIx_PHY_MODE = 1, RGMII exhibits the following symptoms: - No signal on RGMII TXD[] - No TX counters increase on the related MAC port. - RX interface works, and data from the CPU through the switch is properly accounted for. Due to the absence of TX counters even for broadcast traffic, we interpreted this as a disabled MAC TX functionality or disabled TX clock for the MAC. This issue was resolved by unsetting Bit 2 on register 0x301, which is undocumented for RGMII. Now, comparing LAN937x documentation with publicly available documentation for other switches, for example KSZ9893R, may give some clue on the undocumented part in the LAN937x datasheet: RGMII Interface: 1 = In-Band Status (IBS) enabled (requires IBS-capable PHY) 0 = IBS disabled The issue likely stems from active IBS mode, confirmed by an article recommending IBS disablement via register 0x302. https://microchip.my.site.com/s/article/LAN937X-The-required-configuration-for-the-external-MAC-port-to-operate-at-RGMII-to-RGMII-1Gbps-link-speed The same effect seems to be achieved by toggling the undocumented 0x301 bit 2. The ksz_set_xmii() function contains existing code to handle this: case PHY_INTERFACE_MODE_RGMII_RXID: data8 |= bitval[P_RGMII_SEL]; /* On KSZ9893, disable RGMII in-band status support */ if (dev->chip_id == KSZ9893_CHIP_ID || dev->chip_id == KSZ8563_CHIP_ID || dev->chip_id == KSZ9563_CHIP_ID) data8 &= ~P_MII_MAC_MODE; break; default: Regards, Oleksij
> Now, comparing LAN937x documentation with publicly available documentation for > other switches, for example KSZ9893R, may give some clue on the undocumented > part in the LAN937x datasheet: > RGMII Interface: > 1 = In-Band Status (IBS) enabled (requires IBS-capable PHY) > 0 = IBS disabled That explains a lot. With the updated commit message, this patch should be fine. Andrew
diff --git a/drivers/net/dsa/microchip/lan937x_main.c b/drivers/net/dsa/microchip/lan937x_main.c index e907a5602035c..b6ef48a655735 100644 --- a/drivers/net/dsa/microchip/lan937x_main.c +++ b/drivers/net/dsa/microchip/lan937x_main.c @@ -217,6 +217,17 @@ void lan937x_config_cpu_port(struct dsa_switch *ds) if (dev->info->cpu_ports & (1 << dp->index)) { dev->cpu_port = dp->index; + /* + * Force RGMII interface into PHY mode, as that's the + * only valid mode, but it may be in MAC mode due to + * incorrect strapping. + */ + if (phy_interface_mode_is_rgmii(dev->ports[dp->index].interface)) { + lan937x_port_cfg(dev, dp->index, + REG_PORT_XMII_CTRL_1, + PORT_MII_MODE_MAC, false); + } + /* enable cpu port */ lan937x_port_setup(dev, dp->index, true); } diff --git a/drivers/net/dsa/microchip/lan937x_reg.h b/drivers/net/dsa/microchip/lan937x_reg.h index 7ecada9240233..e36bcb155f545 100644 --- a/drivers/net/dsa/microchip/lan937x_reg.h +++ b/drivers/net/dsa/microchip/lan937x_reg.h @@ -150,6 +150,9 @@ #define REG_PORT_TX_PHY_CTRL_BASE 0x0280 /* 3 - xMII */ +#define REG_PORT_XMII_CTRL_1 0x0301 +#define PORT_MII_MODE_MAC BIT(2) + #define PORT_SGMII_SEL BIT(7) #define PORT_GRXC_ENABLE BIT(0)