| Message ID | 20240627-k1-01-basic-dt-v2-2-cc06c7555f07@gentoo.org (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | riscv: add initial support for SpacemiT K1 | expand |
On Thu, Jun 27, 2024 at 03:31:16PM +0000, Yixun Lan wrote: > From: Yangyu Chen <cyy@cyyself.name> > > The X60 is RISC-V CPU cores from SpacemiT and currently used in their K1 > SoC. > > Link: https://www.spacemit.com/en/spacemit-x60-core/ > Same comment as v1 here :) With that addressed, Acked-by: Conor Dooley <conor.dooley@microchip.com> Thanks, Conor. > Signed-off-by: Yangyu Chen <cyy@cyyself.name> > Signed-off-by: Yixun Lan <dlan@gentoo.org> > --- > Documentation/devicetree/bindings/riscv/cpus.yaml | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml > index d87dd50f1a4b5..5ad9cb4103356 100644 > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml > @@ -46,6 +46,7 @@ properties: > - sifive,u7 > - sifive,u74 > - sifive,u74-mc > + - spacemit,x60 > - thead,c906 > - thead,c910 > - thead,c920 > > -- > 2.45.2 >
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml index d87dd50f1a4b5..5ad9cb4103356 100644 --- a/Documentation/devicetree/bindings/riscv/cpus.yaml +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml @@ -46,6 +46,7 @@ properties: - sifive,u7 - sifive,u74 - sifive,u74-mc + - spacemit,x60 - thead,c906 - thead,c910 - thead,c920