mbox series

[v2,0/4] crypto: sun8i-ce: add Allwinner H616 support

Message ID 20240624232110.9817-1-andre.przywara@arm.com (mailing list archive)
Headers show
Series crypto: sun8i-ce: add Allwinner H616 support | expand

Message

Andre Przywara June 24, 2024, 11:21 p.m. UTC
This is an update to the H616 crypto engine support, with the sparse
warning fixed and the accrued tags added.
========================

This series adds support for the crypto engine in the Allwinner H616
SoC. The IP and its capabilities are very similar to the H6, with the
major difference of the DMA engine supporting 34 bit wide addresses.
This is achieved by just shifting every address by 2 bits in the DMA
descriptors; Allwinner calls this "word addresses".
Patch 2/4 adds support for this by wrapping every address access in a
function that does the shift as needed. Patch 1/4 adds the new
compatible string to the binding, patch 3/4 adds that string to the
driver and enables the address shift for it. The final patch 4/4 adds
the DT node to the SoC .dtsi. Since this is an internal peripheral,
it's always enabled.

Corentin's cryptotest passed for me, though I haven't checked how fast
it is and if it really brings an advantage performance-wise, but maybe
people find it useful to offload that from the CPU cores.
One immediate advantage is the availability of the TRNG device, which
helps to feed the kernel's entropy pool much faster - typically before
we reach userland. Without the driver this sometimes takes minutes, and
delays workloads that rely on the entropy pool.

Please have a look and comment!

Cheers,
Andre

Changelog v1 ... v2:
- fix sparse warning by treating writel() call differently (2/4)
- add Acks, R-b and Tested-by: tags

Andre Przywara (4):
  dt-bindings: crypto: sun8i-ce: Add compatible for H616
  crypto: sun8i-ce - wrap accesses to descriptor address fields
  crypto: sun8i-ce - add Allwinner H616 support
  arm64: dts: allwinner: h616: add crypto engine node

 .../bindings/crypto/allwinner,sun8i-ce.yaml   |  2 ++
 .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 +++++++
 .../allwinner/sun8i-ce/sun8i-ce-cipher.c      |  8 +++---
 .../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 28 ++++++++++++++++++-
 .../crypto/allwinner/sun8i-ce/sun8i-ce-hash.c |  6 ++--
 .../crypto/allwinner/sun8i-ce/sun8i-ce-prng.c |  6 ++--
 .../crypto/allwinner/sun8i-ce/sun8i-ce-trng.c |  2 +-
 drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h  | 15 ++++++++++
 8 files changed, 65 insertions(+), 12 deletions(-)

Comments

Herbert Xu July 6, 2024, 12:48 a.m. UTC | #1
On Tue, Jun 25, 2024 at 12:21:06AM +0100, Andre Przywara wrote:
> This is an update to the H616 crypto engine support, with the sparse
> warning fixed and the accrued tags added.
> ========================
> 
> This series adds support for the crypto engine in the Allwinner H616
> SoC. The IP and its capabilities are very similar to the H6, with the
> major difference of the DMA engine supporting 34 bit wide addresses.
> This is achieved by just shifting every address by 2 bits in the DMA
> descriptors; Allwinner calls this "word addresses".
> Patch 2/4 adds support for this by wrapping every address access in a
> function that does the shift as needed. Patch 1/4 adds the new
> compatible string to the binding, patch 3/4 adds that string to the
> driver and enables the address shift for it. The final patch 4/4 adds
> the DT node to the SoC .dtsi. Since this is an internal peripheral,
> it's always enabled.
> 
> Corentin's cryptotest passed for me, though I haven't checked how fast
> it is and if it really brings an advantage performance-wise, but maybe
> people find it useful to offload that from the CPU cores.
> One immediate advantage is the availability of the TRNG device, which
> helps to feed the kernel's entropy pool much faster - typically before
> we reach userland. Without the driver this sometimes takes minutes, and
> delays workloads that rely on the entropy pool.
> 
> Please have a look and comment!
> 
> Cheers,
> Andre
> 
> Changelog v1 ... v2:
> - fix sparse warning by treating writel() call differently (2/4)
> - add Acks, R-b and Tested-by: tags
> 
> Andre Przywara (4):
>   dt-bindings: crypto: sun8i-ce: Add compatible for H616
>   crypto: sun8i-ce - wrap accesses to descriptor address fields
>   crypto: sun8i-ce - add Allwinner H616 support
>   arm64: dts: allwinner: h616: add crypto engine node
> 
>  .../bindings/crypto/allwinner,sun8i-ce.yaml   |  2 ++
>  .../arm64/boot/dts/allwinner/sun50i-h616.dtsi | 10 +++++++
>  .../allwinner/sun8i-ce/sun8i-ce-cipher.c      |  8 +++---
>  .../crypto/allwinner/sun8i-ce/sun8i-ce-core.c | 28 ++++++++++++++++++-
>  .../crypto/allwinner/sun8i-ce/sun8i-ce-hash.c |  6 ++--
>  .../crypto/allwinner/sun8i-ce/sun8i-ce-prng.c |  6 ++--
>  .../crypto/allwinner/sun8i-ce/sun8i-ce-trng.c |  2 +-
>  drivers/crypto/allwinner/sun8i-ce/sun8i-ce.h  | 15 ++++++++++
>  8 files changed, 65 insertions(+), 12 deletions(-)
> 
> -- 
> 2.39.4

Patches 1-3 applied.  Thanks.
Chen-Yu Tsai July 10, 2024, 6:12 p.m. UTC | #2
On Tue, 25 Jun 2024 00:21:06 +0100, Andre Przywara wrote:
> This is an update to the H616 crypto engine support, with the sparse
> warning fixed and the accrued tags added.
> ========================
> 
> This series adds support for the crypto engine in the Allwinner H616
> SoC. The IP and its capabilities are very similar to the H6, with the
> major difference of the DMA engine supporting 34 bit wide addresses.
> This is achieved by just shifting every address by 2 bits in the DMA
> descriptors; Allwinner calls this "word addresses".
> Patch 2/4 adds support for this by wrapping every address access in a
> function that does the shift as needed. Patch 1/4 adds the new
> compatible string to the binding, patch 3/4 adds that string to the
> driver and enables the address shift for it. The final patch 4/4 adds
> the DT node to the SoC .dtsi. Since this is an internal peripheral,
> it's always enabled.
> 
> [...]

Applied to sunxi/dt-for-6.11 in sunxi/linux.git, thanks!

[4/4] arm64: dts: allwinner: h616: add crypto engine node
      https://git.kernel.org/sunxi/linux/c/6ed9a85f1c44

Best regards,