| Message ID | 20240710094149.13299-1-quic_vdadhani@quicinc.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [v1] arm64: dts: qcom: sa8775p: Add UART node | expand |
On 10/07/2024 11:41, Viken Dadhaniya wrote: > Add missing UART configuration for sa8775. > > Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> > --- > arch/arm64/boot/dts/qcom/sa8775p.dtsi | 231 ++++++++++++++++++++++++++ > 1 file changed, 231 insertions(+) > > diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > index 23f1b2e5e624..c107ee40341d 100644 > --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi > +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi > @@ -1,6 +1,7 @@ > // SPDX-License-Identifier: BSD-3-Clause > /* > * Copyright (c) 2023, Linaro Limited > + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. > */ > > #include <dt-bindings/interconnect/qcom,icc.h> > @@ -657,6 +658,21 @@ > status = "disabled"; > }; > > + uart14: serial@880000 { > + compatible = "qcom,geni-uart"; > + reg = <0x0 0x00880000 0x0 0x4000>; > + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; > + clock-names = "se"; > + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS > + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, > + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS > + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; > + interconnect-names = "qup-core", "qup-config"; > + power-domains = <&rpmhpd SA8775P_CX>; All the clocks, interconenct and power domains look to me questionable. AFAIK, most of it (if not all) is going to be removed. Best regards, Krzysztof
On 10.07.2024 11:47 AM, Krzysztof Kozlowski wrote: > On 10/07/2024 11:41, Viken Dadhaniya wrote: >> Add missing UART configuration for sa8775. >> >> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> >> --- >> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 231 ++++++++++++++++++++++++++ >> 1 file changed, 231 insertions(+) >> >> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> index 23f1b2e5e624..c107ee40341d 100644 >> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >> @@ -1,6 +1,7 @@ >> // SPDX-License-Identifier: BSD-3-Clause >> /* >> * Copyright (c) 2023, Linaro Limited >> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. >> */ >> >> #include <dt-bindings/interconnect/qcom,icc.h> >> @@ -657,6 +658,21 @@ >> status = "disabled"; >> }; >> >> + uart14: serial@880000 { >> + compatible = "qcom,geni-uart"; >> + reg = <0x0 0x00880000 0x0 0x4000>; >> + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; >> + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; >> + clock-names = "se"; >> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; >> + interconnect-names = "qup-core", "qup-config"; >> + power-domains = <&rpmhpd SA8775P_CX>; > > All the clocks, interconenct and power domains look to me questionable. > AFAIK, most of it (if not all) is going to be removed. Yeah.. I'm lukewarm on accepting any sa8775p changes until that qcs9100(?) situation is squared out first Konrad
On 7/10/2024 4:09 PM, Konrad Dybcio wrote: > On 10.07.2024 11:47 AM, Krzysztof Kozlowski wrote: >> On 10/07/2024 11:41, Viken Dadhaniya wrote: >>> Add missing UART configuration for sa8775. >>> >>> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 231 ++++++++++++++++++++++++++ >>> 1 file changed, 231 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> index 23f1b2e5e624..c107ee40341d 100644 >>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> @@ -1,6 +1,7 @@ >>> // SPDX-License-Identifier: BSD-3-Clause >>> /* >>> * Copyright (c) 2023, Linaro Limited >>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. >>> */ >>> >>> #include <dt-bindings/interconnect/qcom,icc.h> >>> @@ -657,6 +658,21 @@ >>> status = "disabled"; >>> }; >>> >>> + uart14: serial@880000 { >>> + compatible = "qcom,geni-uart"; >>> + reg = <0x0 0x00880000 0x0 0x4000>; >>> + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; >>> + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; >>> + clock-names = "se"; >>> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >>> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >>> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; >>> + interconnect-names = "qup-core", "qup-config"; >>> + power-domains = <&rpmhpd SA8775P_CX>; >> >> All the clocks, interconenct and power domains look to me questionable. >> AFAIK, most of it (if not all) is going to be removed. > > Yeah.. I'm lukewarm on accepting any sa8775p changes until that qcs9100(?) > situation is squared out first > > Konrad Thanks for clarification. Please help to sign-off or let me know in case of any concern.
On 11/07/2024 07:04, Viken Dadhaniya wrote: >>>> + clock-names = "se"; >>>> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >>>> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >>>> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; >>>> + interconnect-names = "qup-core", "qup-config"; >>>> + power-domains = <&rpmhpd SA8775P_CX>; >>> >>> All the clocks, interconenct and power domains look to me questionable. >>> AFAIK, most of it (if not all) is going to be removed. >> >> Yeah.. I'm lukewarm on accepting any sa8775p changes until that qcs9100(?) >> situation is squared out first >> >> Konrad > > Thanks for clarification. Please help to sign-off or let me know in case > of any concern. I think I was quite explicit, so I feel above suggestion as still pushing your choice even though to reviewers gave you their opinion. In such case: No, NAK, for the reasons stated above. Best regards, Krzysztof
On 7/11/2024 11:47 AM, Krzysztof Kozlowski wrote: > On 11/07/2024 07:04, Viken Dadhaniya wrote: >>>>> + clock-names = "se"; >>>>> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >>>>> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >>>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >>>>> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; >>>>> + interconnect-names = "qup-core", "qup-config"; >>>>> + power-domains = <&rpmhpd SA8775P_CX>; >>>> >>>> All the clocks, interconenct and power domains look to me questionable. >>>> AFAIK, most of it (if not all) is going to be removed. >>> >>> Yeah.. I'm lukewarm on accepting any sa8775p changes until that qcs9100(?) >>> situation is squared out first >>> >>> Konrad >> >> Thanks for clarification. Please help to sign-off or let me know in case >> of any concern. > > I think I was quite explicit, so I feel above suggestion as still > pushing your choice even though to reviewers gave you their opinion. > > In such case: > > No, NAK, for the reasons stated above. > > Best regards, > Krzysztof > Sure, taken the notes from both of you. Shall we wait for the shifting of DTSI file from sc8775p to qcs9100 ? OR is there any other way to move ahead ? Please suggest, we shall do whatever guidance from you both.
On 12/07/2024 11:32, Viken Dadhaniya wrote: > > > On 7/11/2024 11:47 AM, Krzysztof Kozlowski wrote: >> On 11/07/2024 07:04, Viken Dadhaniya wrote: >>>>>> + clock-names = "se"; >>>>>> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >>>>>> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >>>>>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >>>>>> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; >>>>>> + interconnect-names = "qup-core", "qup-config"; >>>>>> + power-domains = <&rpmhpd SA8775P_CX>; >>>>> >>>>> All the clocks, interconenct and power domains look to me questionable. >>>>> AFAIK, most of it (if not all) is going to be removed. >>>> >>>> Yeah.. I'm lukewarm on accepting any sa8775p changes until that qcs9100(?) >>>> situation is squared out first >>>> >>>> Konrad >>> >>> Thanks for clarification. Please help to sign-off or let me know in case >>> of any concern. >> >> I think I was quite explicit, so I feel above suggestion as still >> pushing your choice even though to reviewers gave you their opinion. >> >> In such case: >> >> No, NAK, for the reasons stated above. >> >> Best regards, >> Krzysztof >> > > Sure, taken the notes from both of you. > Shall we wait for the shifting of DTSI file from sc8775p to qcs9100 ? > OR is there any other way to move ahead ? > Please suggest, we shall do whatever guidance from you both. Do not add code which we already know that it is incorrect or incomplete. Instead align with your colleagues about proper upstreaming of this platform. I am not going to sign off such patches. Best regards, Krzysztof
On 7/10/2024 6:39 PM, Konrad Dybcio wrote: > On 10.07.2024 11:47 AM, Krzysztof Kozlowski wrote: >> On 10/07/2024 11:41, Viken Dadhaniya wrote: >>> Add missing UART configuration for sa8775. >>> >>> Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> >>> --- >>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 231 ++++++++++++++++++++++++++ >>> 1 file changed, 231 insertions(+) >>> >>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> index 23f1b2e5e624..c107ee40341d 100644 >>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi >>> @@ -1,6 +1,7 @@ >>> // SPDX-License-Identifier: BSD-3-Clause >>> /* >>> * Copyright (c) 2023, Linaro Limited >>> + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. >>> */ >>> >>> #include <dt-bindings/interconnect/qcom,icc.h> >>> @@ -657,6 +658,21 @@ >>> status = "disabled"; >>> }; >>> >>> + uart14: serial@880000 { >>> + compatible = "qcom,geni-uart"; >>> + reg = <0x0 0x00880000 0x0 0x4000>; >>> + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; >>> + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; >>> + clock-names = "se"; >>> + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS >>> + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, >>> + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS >>> + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; >>> + interconnect-names = "qup-core", "qup-config"; >>> + power-domains = <&rpmhpd SA8775P_CX>; >> >> All the clocks, interconenct and power domains look to me questionable. >> AFAIK, most of it (if not all) is going to be removed. > > Yeah.. I'm lukewarm on accepting any sa8775p changes until that qcs9100(?) > situation is squared out first > > Konrad After considering the feedback provided on the subject, We have decided to keep current SA8775p compatible and ABI compatibility in drivers. Therefore, this patch is still needed, please continue to review this patch. Thank you for your input.
diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi index 23f1b2e5e624..c107ee40341d 100644 --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi @@ -1,6 +1,7 @@ // SPDX-License-Identifier: BSD-3-Clause /* * Copyright (c) 2023, Linaro Limited + * Copyright (c) 2024 Qualcomm Innovation Center, Inc. All rights reserved. */ #include <dt-bindings/interconnect/qcom,icc.h> @@ -657,6 +658,21 @@ status = "disabled"; }; + uart14: serial@880000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00880000 0x0 0x4000>; + interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c15: i2c@884000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x884000 0x0 0x4000>; @@ -699,6 +715,21 @@ status = "disabled"; }; + uart15: serial@884000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00884000 0x0 0x4000>; + interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c16: i2c@888000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x888000 0x0 0x4000>; @@ -741,6 +772,21 @@ status = "disabled"; }; + uart16: serial@888000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00888000 0x0 0x4000>; + interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c17: i2c@88c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x88c000 0x0 0x4000>; @@ -840,6 +886,21 @@ status = "disabled"; }; + uart18: serial@890000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00890000 0x0 0x4000>; + interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c19: i2c@894000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x894000 0x0 0x4000>; @@ -882,6 +943,21 @@ status = "disabled"; }; + uart19: serial@894000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00894000 0x0 0x4000>; + interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c20: i2c@898000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x898000 0x0 0x4000>; @@ -923,6 +999,22 @@ power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + uart20: serial@898000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00898000 0x0 0x4000>; + interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP2_S6_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + }; qupv3_id_0: geniqup@9c0000 { @@ -979,6 +1071,21 @@ status = "disabled"; }; + uart0: serial@980000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x980000 0x0 0x4000>; + interrupts = <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c1: i2c@984000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x984000 0x0 0x4000>; @@ -1021,6 +1128,21 @@ status = "disabled"; }; + uart1: serial@984000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x984000 0x0 0x4000>; + interrupts = <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c2: i2c@988000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x988000 0x0 0x4000>; @@ -1063,6 +1185,21 @@ status = "disabled"; }; + uart2: serial@988000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x988000 0x0 0x4000>; + interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c3: i2c@98c000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x98c000 0x0 0x4000>; @@ -1105,6 +1242,21 @@ status = "disabled"; }; + uart3: serial@98c000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x98c000 0x0 0x4000>; + interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c4: i2c@990000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x990000 0x0 0x4000>; @@ -1147,6 +1299,21 @@ status = "disabled"; }; + uart4: serial@990000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x990000 0x0 0x4000>; + interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; + clock-names = "se"; + interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_0 QCOM_ICC_TAG_ALWAYS>; + interconnect-names = "qup-core", "qup-config"; + power-domains = <&rpmhpd SA8775P_CX>; + status = "disabled"; + }; + i2c5: i2c@994000 { compatible = "qcom,geni-i2c"; reg = <0x0 0x994000 0x0 0x4000>; @@ -1259,6 +1426,22 @@ status = "disabled"; }; + uart7: serial@a80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a80000 0x0 0x4000>; + interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + i2c8: i2c@a84000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa84000 0x0 0x4000>; @@ -1301,6 +1484,22 @@ status = "disabled"; }; + uart8: serial@a84000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a84000 0x0 0x4000>; + interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + i2c9: i2c@a88000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa88000 0x0 0x4000>; @@ -1458,6 +1657,22 @@ status = "disabled"; }; + uart11: serial@a90000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00a90000 0x0 0x4000>; + interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ALWAYS>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; + i2c12: i2c@a94000 { compatible = "qcom,geni-i2c"; reg = <0x0 0xa94000 0x0 0x4000>; @@ -1590,6 +1805,22 @@ power-domains = <&rpmhpd SA8775P_CX>; status = "disabled"; }; + + uart21: serial@b80000 { + compatible = "qcom,geni-uart"; + reg = <0x0 0x00b80000 0x0 0x4000>; + interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "se"; + clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; + interconnect-names = "qup-core", "qup-config"; + interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS + &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS + &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ALWAYS>; + power-domains = <&rpmhpd SA8775P_CX>; + operating-points-v2 = <&qup_opp_table_100mhz>; + status = "disabled"; + }; }; rng: rng@10d2000 {
Add missing UART configuration for sa8775. Signed-off-by: Viken Dadhaniya <quic_vdadhani@quicinc.com> --- arch/arm64/boot/dts/qcom/sa8775p.dtsi | 231 ++++++++++++++++++++++++++ 1 file changed, 231 insertions(+)