| Message ID | 20240710-topic-barman-v1-1-5f63fca8d0fc@linaro.org (mailing list archive) |
|---|---|
| State | Accepted |
| Headers | show |
| Series | arm64: dts: qcom: x1e80100: Fix up BAR spaces | expand |
On 24-07-10 16:07:23, Konrad Dybcio wrote: > The 32-bit BAR spaces are reaching outside their assigned register > regions. Shrink them to match their actual sizes. > While at it, unify the style. > > Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 7bca5fcd7d52..bc5b4f5ea127 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -2895,9 +2895,9 @@ pcie6a: pci@1bf8000 { > "mhi"; > #address-cells = <3>; > #size-cells = <2>; > - ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, > - <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; > - bus-range = <0 0xff>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, > + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x1d00000>; > + bus-range = <0x00 0xff>; > > dma-coherent; > > @@ -3016,8 +3016,8 @@ pcie4: pci@1c08000 { > "mhi"; > #address-cells = <3>; > #size-cells = <2>; > - ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, > - <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, > + <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; > bus-range = <0x00 0xff>; > > dma-coherent; > > --- > base-commit: 0b58e108042b0ed28a71cd7edf5175999955b233 > change-id: 20240710-topic-barman-57a52f7de103 > > Best regards, > -- > Konrad Dybcio <konrad.dybcio@linaro.org> >
On 24-07-10 16:07:23, Konrad Dybcio wrote: > The 32-bit BAR spaces are reaching outside their assigned register > regions. Shrink them to match their actual sizes. > While at it, unify the style. > > Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Also tested on CRD, so: Tested-by: Abel Vesa <abel.vesa@linaro.org> > --- > arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 +++++----- > 1 file changed, 5 insertions(+), 5 deletions(-) > > diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > index 7bca5fcd7d52..bc5b4f5ea127 100644 > --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi > +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi > @@ -2895,9 +2895,9 @@ pcie6a: pci@1bf8000 { > "mhi"; > #address-cells = <3>; > #size-cells = <2>; > - ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, > - <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; > - bus-range = <0 0xff>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, > + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x1d00000>; > + bus-range = <0x00 0xff>; > > dma-coherent; > > @@ -3016,8 +3016,8 @@ pcie4: pci@1c08000 { > "mhi"; > #address-cells = <3>; > #size-cells = <2>; > - ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, > - <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; > + ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, > + <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; > bus-range = <0x00 0xff>; > > dma-coherent; > > --- > base-commit: 0b58e108042b0ed28a71cd7edf5175999955b233 > change-id: 20240710-topic-barman-57a52f7de103 > > Best regards, > -- > Konrad Dybcio <konrad.dybcio@linaro.org> >
On Wed, Jul 10, 2024 at 04:07:23PM +0200, Konrad Dybcio wrote: > The 32-bit BAR spaces are reaching outside their assigned register > regions. Shrink them to match their actual sizes. > While at it, unify the style. > > Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") > Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> This one seems to have fallen through the cracks. Bjorn, can you pick it up or do you want Konrad to resend? Johan
On Wed, 10 Jul 2024 16:07:23 +0200, Konrad Dybcio wrote: > The 32-bit BAR spaces are reaching outside their assigned register > regions. Shrink them to match their actual sizes. > While at it, unify the style. > > Applied, thanks! [1/1] arm64: dts: qcom: x1e80100: Fix up BAR spaces commit: 7af1418500124150f9fd24e1a5b9c288771df271 Best regards,
diff --git a/arch/arm64/boot/dts/qcom/x1e80100.dtsi b/arch/arm64/boot/dts/qcom/x1e80100.dtsi index 7bca5fcd7d52..bc5b4f5ea127 100644 --- a/arch/arm64/boot/dts/qcom/x1e80100.dtsi +++ b/arch/arm64/boot/dts/qcom/x1e80100.dtsi @@ -2895,9 +2895,9 @@ pcie6a: pci@1bf8000 { "mhi"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0 0x00000000 0 0x70200000 0 0x100000>, - <0x02000000 0 0x70300000 0 0x70300000 0 0x3d00000>; - bus-range = <0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x70200000 0x0 0x100000>, + <0x02000000 0x0 0x70300000 0x0 0x70300000 0x0 0x1d00000>; + bus-range = <0x00 0xff>; dma-coherent; @@ -3016,8 +3016,8 @@ pcie4: pci@1c08000 { "mhi"; #address-cells = <3>; #size-cells = <2>; - ranges = <0x01000000 0 0x00000000 0 0x7c200000 0 0x100000>, - <0x02000000 0 0x7c300000 0 0x7c300000 0 0x3d00000>; + ranges = <0x01000000 0x0 0x00000000 0x0 0x7c200000 0x0 0x100000>, + <0x02000000 0x0 0x7c300000 0x0 0x7c300000 0x0 0x1d00000>; bus-range = <0x00 0xff>; dma-coherent;
The 32-bit BAR spaces are reaching outside their assigned register regions. Shrink them to match their actual sizes. While at it, unify the style. Fixes: 5eb83fc10289 ("arm64: dts: qcom: x1e80100: Add PCIe nodes") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> --- arch/arm64/boot/dts/qcom/x1e80100.dtsi | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) --- base-commit: 0b58e108042b0ed28a71cd7edf5175999955b233 change-id: 20240710-topic-barman-57a52f7de103 Best regards,