diff mbox series

[net-next,V2,01/10] net/mlx5: IFC updates for SF max IO EQs

Message ID 20240708080025.1593555-2-tariqt@nvidia.com (mailing list archive)
State Changes Requested
Delegated to: Netdev Maintainers
Headers show
Series mlx5 misc patches 2023-07-08 | expand

Checks

Context Check Description
netdev/series_format success Posting correctly formatted
netdev/tree_selection success Clearly marked for net-next
netdev/ynl success Generated files up to date; no warnings/errors; no diff in generated;
netdev/fixes_present success Fixes tag not required for -next series
netdev/header_inline success No static functions without inline keyword in header files
netdev/build_32bit success Errors and warnings before: 816 this patch: 816
netdev/build_tools success Errors and warnings before: 0 this patch: 0
netdev/cc_maintainers warning 1 maintainers not CCed: linux-rdma@vger.kernel.org
netdev/build_clang success Errors and warnings before: 821 this patch: 821
netdev/verify_signedoff success Signed-off-by tag matches author and committer
netdev/deprecated_api success None detected
netdev/check_selftest success No net selftest shell script
netdev/verify_fixes success No Fixes tag
netdev/build_allmodconfig_warn success Errors and warnings before: 824 this patch: 824
netdev/checkpatch success total: 0 errors, 0 warnings, 0 checks, 10 lines checked
netdev/build_clang_rust success No Rust files in patch. Skipping build
netdev/kdoc success Errors and warnings before: 0 this patch: 0
netdev/source_inline success Was 0 now: 0
netdev/contest success net-next-2024-07-08--15-00 (tests: 694)

Commit Message

Tariq Toukan July 8, 2024, 8 a.m. UTC 
From: Daniel Jurgens <danielj@nvidia.com>

Expose a new cap sf_eq_usage. The vhca_resource_manager can write this
cap, indicating the SF driver should use max_num_eqs_24b to determine
how many EQs to use.

Signed-off-by: Daniel Jurgens <danielj@nvidia.com>
Reviewed-by: William Tu <witu@nvidia.com>
Signed-off-by: Tariq Toukan <tariqt@nvidia.com>
---
 include/linux/mlx5/mlx5_ifc.h | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

Comments

Jakub Kicinski July 10, 2024, 1:54 a.m. UTC | #1 
On Mon, 8 Jul 2024 11:00:16 +0300 Tariq Toukan wrote:
> From: Daniel Jurgens <danielj@nvidia.com>
> 
> Expose a new cap sf_eq_usage. The vhca_resource_manager can write this
> cap, indicating the SF driver should use max_num_eqs_24b to determine
> how many EQs to use.

How does vhca_resource_manager write this cap?
Dan Jurgens July 10, 2024, 1:08 p.m. UTC | #2 
> From: Jakub Kicinski <kuba@kernel.org>
> Sent: Tuesday, July 9, 2024 8:55 PM
> On Mon, 8 Jul 2024 11:00:16 +0300 Tariq Toukan wrote:
> > From: Daniel Jurgens <danielj@nvidia.com>
> >
> > Expose a new cap sf_eq_usage. The vhca_resource_manager can write this
> > cap, indicating the SF driver should use max_num_eqs_24b to determine
> > how many EQs to use.
> 
> How does vhca_resource_manager write this cap?

In most literal sense, MLX5_SET(cmd_hca_cap_2, hca_caps, sf_eq_usage, 1);. 

But getting there flows through:
devlink port function set pci/0000:08:00.0/32768 max_io_eqs 32

See patch 02/10.
Jakub Kicinski July 11, 2024, 12:44 a.m. UTC | #3 
On Wed, 10 Jul 2024 13:08:31 +0000 Dan Jurgens wrote:
> > > Expose a new cap sf_eq_usage. The vhca_resource_manager can write this
> > > cap, indicating the SF driver should use max_num_eqs_24b to determine
> > > how many EQs to use.  
> > 
> > How does vhca_resource_manager write this cap?  
> 
> In most literal sense, MLX5_SET(cmd_hca_cap_2, hca_caps, sf_eq_usage, 1);. 
> 
> But getting there flows through:
> devlink port function set pci/0000:08:00.0/32768 max_io_eqs 32

Makes sense, include in the commit message, please?
diff mbox series

Patch

diff --git a/include/linux/mlx5/mlx5_ifc.h b/include/linux/mlx5/mlx5_ifc.h
index fdad0071d599..360d42f041b0 100644
--- a/include/linux/mlx5/mlx5_ifc.h
+++ b/include/linux/mlx5/mlx5_ifc.h
@@ -1994,7 +1994,9 @@  struct mlx5_ifc_cmd_hca_cap_2_bits {
 	u8	   migration_tracking_state[0x1];
 	u8	   reserved_at_ca[0x6];
 	u8	   migration_in_chunks[0x1];
-	u8	   reserved_at_d1[0xf];
+	u8	   reserved_at_d1[0x1];
+	u8	   sf_eq_usage[0x1];
+	u8	   reserved_at_d3[0xd];
 
 	u8	   cross_vhca_object_to_object_supported[0x20];