| Message ID | 20240628152348.61133-2-iansdannapel@gmail.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Summary of changes | expand |
Hi,
kernel test robot noticed the following build warnings:
https://git-scm.com/docs/git-format-patch#_base_tree_information]
url: https://github.com/intel-lab-lkp/linux/commits/iansdannapel-gmail-com/fpga-Add-Efinix-Trion-Titanium-serial-SPI-programming-driver/20240630-044745
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link: https://lore.kernel.org/r/20240628152348.61133-2-iansdannapel%40gmail.com
patch subject: [PATCH v2 1/3] fpga: Add Efinix Trion & Titanium serial SPI programming driver
config: powerpc-randconfig-r081-20240701 (https://download.01.org/0day-ci/archive/20240703/202407030525.VHF3He6K-lkp@intel.com/config)
compiler: clang version 14.0.6 (https://github.com/llvm/llvm-project f28c006a5895fc0e329fe15fead81e37457cb1d1)
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Reported-by: Dan Carpenter <dan.carpenter@linaro.org>
| Closes: https://lore.kernel.org/r/202407030525.VHF3He6K-lkp@intel.com/
smatch warnings:
drivers/fpga/efinix-trion-spi-passive.c:174 efinix_spi_probe() warn: passing zero to 'PTR_ERR'
vim +/PTR_ERR +174 drivers/fpga/efinix-trion-spi-passive.c
4c272ecc14b70f Ian Dannapel 2024-06-28 152 static int efinix_spi_probe(struct spi_device *spi)
4c272ecc14b70f Ian Dannapel 2024-06-28 153 {
4c272ecc14b70f Ian Dannapel 2024-06-28 154 struct efinix_spi_conf *conf;
4c272ecc14b70f Ian Dannapel 2024-06-28 155 struct fpga_manager *mgr;
4c272ecc14b70f Ian Dannapel 2024-06-28 156
4c272ecc14b70f Ian Dannapel 2024-06-28 157 conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL);
4c272ecc14b70f Ian Dannapel 2024-06-28 158 if (!conf)
4c272ecc14b70f Ian Dannapel 2024-06-28 159 return -ENOMEM;
4c272ecc14b70f Ian Dannapel 2024-06-28 160
4c272ecc14b70f Ian Dannapel 2024-06-28 161 conf->spi = spi;
4c272ecc14b70f Ian Dannapel 2024-06-28 162
4c272ecc14b70f Ian Dannapel 2024-06-28 163 conf->creset = devm_gpiod_get(&spi->dev, "creset", GPIOD_OUT_HIGH);
4c272ecc14b70f Ian Dannapel 2024-06-28 164 if (IS_ERR(conf->creset))
4c272ecc14b70f Ian Dannapel 2024-06-28 165 return dev_err_probe(&spi->dev, PTR_ERR(conf->creset),
4c272ecc14b70f Ian Dannapel 2024-06-28 166 "Failed to get RESET gpio\n");
4c272ecc14b70f Ian Dannapel 2024-06-28 167
4c272ecc14b70f Ian Dannapel 2024-06-28 168 conf->cs = devm_gpiod_get(&spi->dev, "cs", GPIOD_OUT_HIGH);
4c272ecc14b70f Ian Dannapel 2024-06-28 169 if (IS_ERR(conf->cs))
4c272ecc14b70f Ian Dannapel 2024-06-28 170 return dev_err_probe(&spi->dev, PTR_ERR(conf->cs),
4c272ecc14b70f Ian Dannapel 2024-06-28 171 "Failed to get CHIP_SELECT gpio\n");
4c272ecc14b70f Ian Dannapel 2024-06-28 172
4c272ecc14b70f Ian Dannapel 2024-06-28 173 if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL))
4c272ecc14b70f Ian Dannapel 2024-06-28 @174 return dev_err_probe(&spi->dev, PTR_ERR(conf->cs),
s/conf->cs/-EINVAL/
4c272ecc14b70f Ian Dannapel 2024-06-28 175 "Unsupported SPI mode, set CPHA and CPOL\n");
4c272ecc14b70f Ian Dannapel 2024-06-28 176
4c272ecc14b70f Ian Dannapel 2024-06-28 177 conf->cdone = devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN);
4c272ecc14b70f Ian Dannapel 2024-06-28 178 if (IS_ERR(conf->cdone))
4c272ecc14b70f Ian Dannapel 2024-06-28 179 return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone),
4c272ecc14b70f Ian Dannapel 2024-06-28 180 "Failed to get CDONE gpio\n");
4c272ecc14b70f Ian Dannapel 2024-06-28 181
4c272ecc14b70f Ian Dannapel 2024-06-28 182 mgr = devm_fpga_mgr_register(&spi->dev,
4c272ecc14b70f Ian Dannapel 2024-06-28 183 "Efinix SPI Passive Programming FPGA Manager",
4c272ecc14b70f Ian Dannapel 2024-06-28 184 &efinix_spi_ops, conf);
4c272ecc14b70f Ian Dannapel 2024-06-28 185
4c272ecc14b70f Ian Dannapel 2024-06-28 186 return PTR_ERR_OR_ZERO(mgr);
4c272ecc14b70f Ian Dannapel 2024-06-28 187 }
On Fri, Jun 28, 2024 at 05:23:46PM +0200, iansdannapel@gmail.com wrote: > From: Ian Dannapel <iansdannapel@gmail.com> > Please don't reply to the previous series when you post a new version. > Add a new driver for loading binary firmware using "SPI passive Loading to some nvram or reporgraming to FPGA logic blocks. > programming" on Efinix FPGAs. > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com> > --- > drivers/fpga/Kconfig | 8 + > drivers/fpga/Makefile | 1 + > drivers/fpga/efinix-trion-spi-passive.c | 219 ++++++++++++++++++++++++ > 3 files changed, 228 insertions(+) > create mode 100644 drivers/fpga/efinix-trion-spi-passive.c > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > index 37b35f58f0df..25579510e49e 100644 > --- a/drivers/fpga/Kconfig > +++ b/drivers/fpga/Kconfig > @@ -83,6 +83,14 @@ config FPGA_MGR_XILINX_SPI > FPGA manager driver support for Xilinx FPGA configuration > over slave serial interface. > > +config FPGA_MGR_EFINIX_SPI > + tristate "Efinix FPGA configuration over SPI passive" > + depends on SPI > + help > + This option enables support for the FPGA manager driver to > + configure Efinix Trion and Titanium Series FPGAs over SPI > + using passive serial mode. > + > config FPGA_MGR_ICE40_SPI > tristate "Lattice iCE40 SPI" > depends on OF && SPI > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > index aeb89bb13517..1a95124ff847 100644 > --- a/drivers/fpga/Makefile > +++ b/drivers/fpga/Makefile > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o > obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-trion-spi-passive.o > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o > obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o > diff --git a/drivers/fpga/efinix-trion-spi-passive.c b/drivers/fpga/efinix-trion-spi-passive.c > new file mode 100644 > index 000000000000..eb2592e788b9 > --- /dev/null > +++ b/drivers/fpga/efinix-trion-spi-passive.c > @@ -0,0 +1,219 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Trion and Titanium Series FPGA SPI Passive Programming Driver > + * > + * Copyright (C) 2024 iris-GmbH infrared & intelligent sensors > + * > + * Ian Dannapel <iansdannapel@gmail.com> > + * > + * Manage Efinix FPGA firmware that is loaded over SPI using > + * the serial configuration interface. > + */ > + > +#include <linux/delay.h> > +#include <linux/device.h> > +#include <linux/fpga/fpga-mgr.h> > +#include <linux/gpio/consumer.h> > +#include <linux/module.h> > +#include <linux/mod_devicetable.h> > +#include <linux/of.h> > +#include <linux/spi/spi.h> > +#include <linux/sizes.h> > + > +struct efinix_spi_conf { > + struct spi_device *spi; > + struct gpio_desc *cdone; > + struct gpio_desc *creset; > + struct gpio_desc *cs; > +}; > + > +static int get_cdone_gpio(struct fpga_manager *mgr) Is it better use 'struct efinix_spi_conf *conf' as parameter? Same for the following functions. > +{ > + struct efinix_spi_conf *conf = mgr->priv; > + int ret; > + > + ret = gpiod_get_value(conf->cdone); > + if (ret < 0) > + dev_err(&mgr->dev, "Error reading CDONE (%d)\n", ret); > + > + return ret; > +} > + > +static void reset(struct fpga_manager *mgr) Please unify the naming of the internal functions. You use 'efinix_spi_apply_clk_cycles()' below. > +{ > + struct efinix_spi_conf *conf = mgr->priv; > + > + gpiod_set_value(conf->creset, 1); > + /* wait tCRESET_N */ > + usleep_range(5, 15); > + gpiod_set_value(conf->creset, 0); > +} > + > +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) > +{ > + struct efinix_spi_conf *conf = mgr->priv; > + > + if (conf->cdone && get_cdone_gpio(mgr) == 1) > + return FPGA_MGR_STATE_OPERATING; > + > + return FPGA_MGR_STATE_UNKNOWN; > +} > + > +static int efinix_spi_apply_clk_cycles(struct fpga_manager *mgr) > +{ > + struct efinix_spi_conf *conf = mgr->priv; > + char data[13] = {0}; > + > + return spi_write(conf->spi, data, sizeof(data)); > +} > + > +static int efinix_spi_write_init(struct fpga_manager *mgr, > + struct fpga_image_info *info, > + const char *buf, size_t count) > +{ > + struct efinix_spi_conf *conf = mgr->priv; > + > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); > + return -EINVAL; > + } > + > + /* reset with chip select active */ > + gpiod_set_value(conf->cs, 1); Why operating chip selective at SPI client driver? Isn't it the job for SPI controller? > + usleep_range(5, 15); > + reset(mgr); > + > + /* wait tDMIN */ > + usleep_range(100, 150); > + > + return 0; > +} > + > +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf, > + size_t count) > +{ > + struct efinix_spi_conf *conf = mgr->priv; > + int ret; > + > + ret = spi_write(conf->spi, buf, count); > + if (ret) { > + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", > + ret); > + return ret; > + } > + > + /* append at least 100 clock cycles */ > + efinix_spi_apply_clk_cycles(mgr); > + > + /* release chip select */ > + gpiod_set_value(conf->cs, 0); Is it correct? What if there is remaining data to write? > + > + return 0; > +} > + > +static int efinix_spi_write_complete(struct fpga_manager *mgr, > + struct fpga_image_info *info) > +{ > + struct efinix_spi_conf *conf = mgr->priv; > + unsigned long timeout = > + jiffies + usecs_to_jiffies(info->config_complete_timeout_us); > + bool expired = false; > + int done; > + > + if (conf->cdone) { > + while (!expired) { > + expired = time_after(jiffies, timeout); > + > + done = get_cdone_gpio(mgr); > + if (done < 0) > + return done; > + > + if (done) > + break; > + } > + } > + > + if (expired) > + return -ETIMEDOUT; > + > + /* wait tUSER */ > + usleep_range(75, 125); > + > + return 0; > +} > + > +static const struct fpga_manager_ops efinix_spi_ops = { > + .state = efinix_spi_state, > + .write_init = efinix_spi_write_init, > + .write = efinix_spi_write, > + .write_complete = efinix_spi_write_complete, > +}; > + > +static int efinix_spi_probe(struct spi_device *spi) > +{ > + struct efinix_spi_conf *conf; > + struct fpga_manager *mgr; > + > + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); > + if (!conf) > + return -ENOMEM; > + > + conf->spi = spi; > + > + conf->creset = devm_gpiod_get(&spi->dev, "creset", GPIOD_OUT_HIGH); > + if (IS_ERR(conf->creset)) > + return dev_err_probe(&spi->dev, PTR_ERR(conf->creset), > + "Failed to get RESET gpio\n"); > + > + conf->cs = devm_gpiod_get(&spi->dev, "cs", GPIOD_OUT_HIGH); > + if (IS_ERR(conf->cs)) > + return dev_err_probe(&spi->dev, PTR_ERR(conf->cs), > + "Failed to get CHIP_SELECT gpio\n"); > + > + if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL)) > + return dev_err_probe(&spi->dev, PTR_ERR(conf->cs), > + "Unsupported SPI mode, set CPHA and CPOL\n"); > + > + conf->cdone = devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN); > + if (IS_ERR(conf->cdone)) > + return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone), > + "Failed to get CDONE gpio\n"); > + > + mgr = devm_fpga_mgr_register(&spi->dev, > + "Efinix SPI Passive Programming FPGA Manager", > + &efinix_spi_ops, conf); > + > + return PTR_ERR_OR_ZERO(mgr); > +} > + > +#ifdef CONFIG_OF > +static const struct of_device_id efnx_spi_of_match[] = { > + { .compatible = "efinix,trion-spi-passive", }, > + { .compatible = "efinix,titanium-spi-passive", }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, efnx_spi_of_match); > +#endif > + > +static const struct spi_device_id efinix_ids[] = { > + { "trion-spi-passive", 0 }, > + { "titanium-spi-passive", 0 }, > + {}, > +}; > +MODULE_DEVICE_TABLE(spi, efinix_ids); > + > + remove the extra blank line. > +static struct spi_driver efinix_spi_passive_driver = { > + .driver = { > + .name = "efinix-fpga-spi-passive", > + .of_match_table = of_match_ptr(efnx_spi_of_match), Is it OK remove CONFIG_OF & of_match_ptr()? Thanks, Yilun > + }, > + .probe = efinix_spi_probe, > + .id_table = efinix_ids, > +}; > + > +module_spi_driver(efinix_spi_passive_driver); > + > +MODULE_LICENSE("GPL"); > +MODULE_AUTHOR("Ian Dannapel <iansdannapel@gmail.com>"); > +MODULE_DESCRIPTION("Load Efinix FPGA firmware over SPI passive"); > -- > 2.34.1 > >
Hi Yilun, thanks for the review. Am Fr., 12. Juli 2024 um 09:00 Uhr schrieb Xu Yilun <yilun.xu@linux.intel.com>: > > On Fri, Jun 28, 2024 at 05:23:46PM +0200, iansdannapel@gmail.com wrote: > > From: Ian Dannapel <iansdannapel@gmail.com> > > > > Please don't reply to the previous series when you post a new version. sure > > > Add a new driver for loading binary firmware using "SPI passive > > Loading to some nvram or reporgraming to FPGA logic blocks. > > > programming" on Efinix FPGAs. > > > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com> > > --- > > drivers/fpga/Kconfig | 8 + > > drivers/fpga/Makefile | 1 + > > drivers/fpga/efinix-trion-spi-passive.c | 219 ++++++++++++++++++++++++ > > 3 files changed, 228 insertions(+) > > create mode 100644 drivers/fpga/efinix-trion-spi-passive.c > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > > index 37b35f58f0df..25579510e49e 100644 > > --- a/drivers/fpga/Kconfig > > +++ b/drivers/fpga/Kconfig > > @@ -83,6 +83,14 @@ config FPGA_MGR_XILINX_SPI > > FPGA manager driver support for Xilinx FPGA configuration > > over slave serial interface. > > > > +config FPGA_MGR_EFINIX_SPI > > + tristate "Efinix FPGA configuration over SPI passive" > > + depends on SPI > > + help > > + This option enables support for the FPGA manager driver to > > + configure Efinix Trion and Titanium Series FPGAs over SPI > > + using passive serial mode. > > + > > config FPGA_MGR_ICE40_SPI > > tristate "Lattice iCE40 SPI" > > depends on OF && SPI > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > > index aeb89bb13517..1a95124ff847 100644 > > --- a/drivers/fpga/Makefile > > +++ b/drivers/fpga/Makefile > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > > obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o > > obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o > > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > > +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-trion-spi-passive.o > > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o > > obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o > > diff --git a/drivers/fpga/efinix-trion-spi-passive.c b/drivers/fpga/efinix-trion-spi-passive.c > > new file mode 100644 > > index 000000000000..eb2592e788b9 > > --- /dev/null > > +++ b/drivers/fpga/efinix-trion-spi-passive.c > > @@ -0,0 +1,219 @@ > > +// SPDX-License-Identifier: GPL-2.0-only > > +/* > > + * Trion and Titanium Series FPGA SPI Passive Programming Driver > > + * > > + * Copyright (C) 2024 iris-GmbH infrared & intelligent sensors > > + * > > + * Ian Dannapel <iansdannapel@gmail.com> > > + * > > + * Manage Efinix FPGA firmware that is loaded over SPI using > > + * the serial configuration interface. > > + */ > > + > > +#include <linux/delay.h> > > +#include <linux/device.h> > > +#include <linux/fpga/fpga-mgr.h> > > +#include <linux/gpio/consumer.h> > > +#include <linux/module.h> > > +#include <linux/mod_devicetable.h> > > +#include <linux/of.h> > > +#include <linux/spi/spi.h> > > +#include <linux/sizes.h> > > + > > +struct efinix_spi_conf { > > + struct spi_device *spi; > > + struct gpio_desc *cdone; > > + struct gpio_desc *creset; > > + struct gpio_desc *cs; > > +}; > > + > > +static int get_cdone_gpio(struct fpga_manager *mgr) > > Is it better use 'struct efinix_spi_conf *conf' as parameter? > > Same for the following functions. > > > +{ > > + struct efinix_spi_conf *conf = mgr->priv; > > + int ret; > > + > > + ret = gpiod_get_value(conf->cdone); > > + if (ret < 0) > > + dev_err(&mgr->dev, "Error reading CDONE (%d)\n", ret); > > + > > + return ret; > > +} > > + > > +static void reset(struct fpga_manager *mgr) > > Please unify the naming of the internal functions. You use > 'efinix_spi_apply_clk_cycles()' below. > > > +{ > > + struct efinix_spi_conf *conf = mgr->priv; > > + > > + gpiod_set_value(conf->creset, 1); > > + /* wait tCRESET_N */ > > + usleep_range(5, 15); > > + gpiod_set_value(conf->creset, 0); > > +} > > + > > +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) > > +{ > > + struct efinix_spi_conf *conf = mgr->priv; > > + > > + if (conf->cdone && get_cdone_gpio(mgr) == 1) > > + return FPGA_MGR_STATE_OPERATING; > > + > > + return FPGA_MGR_STATE_UNKNOWN; > > +} > > + > > +static int efinix_spi_apply_clk_cycles(struct fpga_manager *mgr) > > +{ > > + struct efinix_spi_conf *conf = mgr->priv; > > + char data[13] = {0}; > > + > > + return spi_write(conf->spi, data, sizeof(data)); > > +} > > + > > +static int efinix_spi_write_init(struct fpga_manager *mgr, > > + struct fpga_image_info *info, > > + const char *buf, size_t count) > > +{ > > + struct efinix_spi_conf *conf = mgr->priv; > > + > > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > > + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); > > + return -EINVAL; > > + } > > + > > + /* reset with chip select active */ > > + gpiod_set_value(conf->cs, 1); > > Why operating chip selective at SPI client driver? Isn't it the job for SPI > controller? to enter the passive programming mode, a reset must be executed while the chip select is active. The is controlling the chip select from here, since I expect that the SPI controller to only activate the CS when communicating. > > > + usleep_range(5, 15); > > + reset(mgr); > > + > > + /* wait tDMIN */ > > + usleep_range(100, 150); > > + > > + return 0; > > +} > > + > > +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf, > > + size_t count) > > +{ > > + struct efinix_spi_conf *conf = mgr->priv; > > + int ret; > > + > > + ret = spi_write(conf->spi, buf, count); > > + if (ret) { > > + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", > > + ret); > > + return ret; > > + } > > + > > + /* append at least 100 clock cycles */ > > + efinix_spi_apply_clk_cycles(mgr); > > + > > + /* release chip select */ > > + gpiod_set_value(conf->cs, 0); > > Is it correct? What if there is remaining data to write? I assumed that the spi controller should write complete buffer and decide on the transfer block size, so there shouldn't be any remaining data. Can someone confirm? > > > + > > + return 0; > > +} > > + > > +static int efinix_spi_write_complete(struct fpga_manager *mgr, > > + struct fpga_image_info *info) > > +{ > > + struct efinix_spi_conf *conf = mgr->priv; > > + unsigned long timeout = > > + jiffies + usecs_to_jiffies(info->config_complete_timeout_us); > > + bool expired = false; > > + int done; > > + > > + if (conf->cdone) { > > + while (!expired) { > > + expired = time_after(jiffies, timeout); > > + > > + done = get_cdone_gpio(mgr); > > + if (done < 0) > > + return done; > > + > > + if (done) > > + break; > > + } > > + } > > + > > + if (expired) > > + return -ETIMEDOUT; > > + > > + /* wait tUSER */ > > + usleep_range(75, 125); > > + > > + return 0; > > +} > > + > > +static const struct fpga_manager_ops efinix_spi_ops = { > > + .state = efinix_spi_state, > > + .write_init = efinix_spi_write_init, > > + .write = efinix_spi_write, > > + .write_complete = efinix_spi_write_complete, > > +}; > > + > > +static int efinix_spi_probe(struct spi_device *spi) > > +{ > > + struct efinix_spi_conf *conf; > > + struct fpga_manager *mgr; > > + > > + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); > > + if (!conf) > > + return -ENOMEM; > > + > > + conf->spi = spi; > > + > > + conf->creset = devm_gpiod_get(&spi->dev, "creset", GPIOD_OUT_HIGH); > > + if (IS_ERR(conf->creset)) > > + return dev_err_probe(&spi->dev, PTR_ERR(conf->creset), > > + "Failed to get RESET gpio\n"); > > + > > + conf->cs = devm_gpiod_get(&spi->dev, "cs", GPIOD_OUT_HIGH); > > + if (IS_ERR(conf->cs)) > > + return dev_err_probe(&spi->dev, PTR_ERR(conf->cs), > > + "Failed to get CHIP_SELECT gpio\n"); > > + > > + if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL)) > > + return dev_err_probe(&spi->dev, PTR_ERR(conf->cs), > > + "Unsupported SPI mode, set CPHA and CPOL\n"); > > + > > + conf->cdone = devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN); > > + if (IS_ERR(conf->cdone)) > > + return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone), > > + "Failed to get CDONE gpio\n"); > > + > > + mgr = devm_fpga_mgr_register(&spi->dev, > > + "Efinix SPI Passive Programming FPGA Manager", > > + &efinix_spi_ops, conf); > > + > > + return PTR_ERR_OR_ZERO(mgr); > > +} > > + > > +#ifdef CONFIG_OF > > +static const struct of_device_id efnx_spi_of_match[] = { > > + { .compatible = "efinix,trion-spi-passive", }, > > + { .compatible = "efinix,titanium-spi-passive", }, > > + {} > > +}; > > +MODULE_DEVICE_TABLE(of, efnx_spi_of_match); > > +#endif > > + > > +static const struct spi_device_id efinix_ids[] = { > > + { "trion-spi-passive", 0 }, > > + { "titanium-spi-passive", 0 }, > > + {}, > > +}; > > +MODULE_DEVICE_TABLE(spi, efinix_ids); > > + > > + > > remove the extra blank line. > > > +static struct spi_driver efinix_spi_passive_driver = { > > + .driver = { > > + .name = "efinix-fpga-spi-passive", > > + .of_match_table = of_match_ptr(efnx_spi_of_match), > > Is it OK remove CONFIG_OF & of_match_ptr()? I don't think it could work without device tree support > > Thanks, > Yilun > > > + }, > > + .probe = efinix_spi_probe, > > + .id_table = efinix_ids, > > +}; > > + > > +module_spi_driver(efinix_spi_passive_driver); > > + > > +MODULE_LICENSE("GPL"); > > +MODULE_AUTHOR("Ian Dannapel <iansdannapel@gmail.com>"); > > +MODULE_DESCRIPTION("Load Efinix FPGA firmware over SPI passive"); > > -- > > 2.34.1 > > > > I will soon prepare a v3 for the rest. Thanks Ian
On Thu, Jul 25, 2024 at 03:44:54PM +0200, Ian Dannapel wrote: > Hi Yilun, thanks for the review. > > Am Fr., 12. Juli 2024 um 09:00 Uhr schrieb Xu Yilun <yilun.xu@linux.intel.com>: > > > > On Fri, Jun 28, 2024 at 05:23:46PM +0200, iansdannapel@gmail.com wrote: > > > From: Ian Dannapel <iansdannapel@gmail.com> > > > > > > > Please don't reply to the previous series when you post a new version. > sure > > > > > Add a new driver for loading binary firmware using "SPI passive > > > > Loading to some nvram or reporgraming to FPGA logic blocks. Sorry for typo, this is a question: Loading to some nvram or reporgraming to FPGA logic blocks? > > > > > programming" on Efinix FPGAs. > > > > > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com> > > > --- > > > drivers/fpga/Kconfig | 8 + > > > drivers/fpga/Makefile | 1 + > > > drivers/fpga/efinix-trion-spi-passive.c | 219 ++++++++++++++++++++++++ > > > 3 files changed, 228 insertions(+) > > > create mode 100644 drivers/fpga/efinix-trion-spi-passive.c > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > > > index 37b35f58f0df..25579510e49e 100644 > > > --- a/drivers/fpga/Kconfig > > > +++ b/drivers/fpga/Kconfig > > > @@ -83,6 +83,14 @@ config FPGA_MGR_XILINX_SPI > > > FPGA manager driver support for Xilinx FPGA configuration > > > over slave serial interface. > > > > > > +config FPGA_MGR_EFINIX_SPI > > > + tristate "Efinix FPGA configuration over SPI passive" > > > + depends on SPI > > > + help > > > + This option enables support for the FPGA manager driver to > > > + configure Efinix Trion and Titanium Series FPGAs over SPI > > > + using passive serial mode. > > > + > > > config FPGA_MGR_ICE40_SPI > > > tristate "Lattice iCE40 SPI" > > > depends on OF && SPI > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > > > index aeb89bb13517..1a95124ff847 100644 > > > --- a/drivers/fpga/Makefile > > > +++ b/drivers/fpga/Makefile > > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > > > obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o > > > obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o > > > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > > > +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-trion-spi-passive.o > > > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o > > > obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o > > > diff --git a/drivers/fpga/efinix-trion-spi-passive.c b/drivers/fpga/efinix-trion-spi-passive.c > > > new file mode 100644 > > > index 000000000000..eb2592e788b9 > > > --- /dev/null > > > +++ b/drivers/fpga/efinix-trion-spi-passive.c > > > @@ -0,0 +1,219 @@ > > > +// SPDX-License-Identifier: GPL-2.0-only > > > +/* > > > + * Trion and Titanium Series FPGA SPI Passive Programming Driver > > > + * > > > + * Copyright (C) 2024 iris-GmbH infrared & intelligent sensors > > > + * > > > + * Ian Dannapel <iansdannapel@gmail.com> > > > + * > > > + * Manage Efinix FPGA firmware that is loaded over SPI using > > > + * the serial configuration interface. > > > + */ > > > + > > > +#include <linux/delay.h> > > > +#include <linux/device.h> > > > +#include <linux/fpga/fpga-mgr.h> > > > +#include <linux/gpio/consumer.h> > > > +#include <linux/module.h> > > > +#include <linux/mod_devicetable.h> > > > +#include <linux/of.h> > > > +#include <linux/spi/spi.h> > > > +#include <linux/sizes.h> > > > + > > > +struct efinix_spi_conf { > > > + struct spi_device *spi; > > > + struct gpio_desc *cdone; > > > + struct gpio_desc *creset; > > > + struct gpio_desc *cs; > > > +}; > > > + > > > +static int get_cdone_gpio(struct fpga_manager *mgr) > > > > Is it better use 'struct efinix_spi_conf *conf' as parameter? > > > > Same for the following functions. > > > > > +{ > > > + struct efinix_spi_conf *conf = mgr->priv; > > > + int ret; > > > + > > > + ret = gpiod_get_value(conf->cdone); > > > + if (ret < 0) > > > + dev_err(&mgr->dev, "Error reading CDONE (%d)\n", ret); > > > + > > > + return ret; > > > +} > > > + > > > +static void reset(struct fpga_manager *mgr) > > > > Please unify the naming of the internal functions. You use > > 'efinix_spi_apply_clk_cycles()' below. > > > > > +{ > > > + struct efinix_spi_conf *conf = mgr->priv; > > > + > > > + gpiod_set_value(conf->creset, 1); > > > + /* wait tCRESET_N */ > > > + usleep_range(5, 15); > > > + gpiod_set_value(conf->creset, 0); > > > +} > > > + > > > +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) > > > +{ > > > + struct efinix_spi_conf *conf = mgr->priv; > > > + > > > + if (conf->cdone && get_cdone_gpio(mgr) == 1) > > > + return FPGA_MGR_STATE_OPERATING; > > > + > > > + return FPGA_MGR_STATE_UNKNOWN; > > > +} > > > + > > > +static int efinix_spi_apply_clk_cycles(struct fpga_manager *mgr) > > > +{ > > > + struct efinix_spi_conf *conf = mgr->priv; > > > + char data[13] = {0}; > > > + > > > + return spi_write(conf->spi, data, sizeof(data)); > > > +} > > > + > > > +static int efinix_spi_write_init(struct fpga_manager *mgr, > > > + struct fpga_image_info *info, > > > + const char *buf, size_t count) > > > +{ > > > + struct efinix_spi_conf *conf = mgr->priv; > > > + > > > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > > > + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); > > > + return -EINVAL; > > > + } > > > + > > > + /* reset with chip select active */ > > > + gpiod_set_value(conf->cs, 1); > > > > Why operating chip selective at SPI client driver? Isn't it the job for SPI > > controller? > to enter the passive programming mode, a reset must be executed while > the chip select is active. > The is controlling the chip select from here, since I expect that the > SPI controller to only activate > the CS when communicating. The concern is, it may conflict with the underlying cs control in spi controller. There are several control flags in struct spi_transfter to affect cs. Is there any chance using them, or try to improve if they doesn't meet your request? > > > > > + usleep_range(5, 15); > > > + reset(mgr); > > > + > > > + /* wait tDMIN */ > > > + usleep_range(100, 150); And these ones, or you could use some delay controls in struct spi_transfer. > > > + > > > + return 0; > > > +} > > > + > > > +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf, > > > + size_t count) > > > +{ > > > + struct efinix_spi_conf *conf = mgr->priv; > > > + int ret; > > > + > > > + ret = spi_write(conf->spi, buf, count); > > > + if (ret) { > > > + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", > > > + ret); > > > + return ret; > > > + } > > > + > > > + /* append at least 100 clock cycles */ > > > + efinix_spi_apply_clk_cycles(mgr); > > > + > > > + /* release chip select */ > > > + gpiod_set_value(conf->cs, 0); > > > > Is it correct? What if there is remaining data to write? > I assumed that the spi controller should write complete buffer and > decide on the transfer block size, > so there shouldn't be any remaining data. Can someone confirm? This is not about spi transfer, it is the fpga_manager_ops.write could be called multiple times during one time reprogramming. Please investigate more about the FPGA mgr core. Thanks, Yilun
Am Sa., 27. Juli 2024 um 18:00 Uhr schrieb Xu Yilun <yilun.xu@linux.intel.com>: > > On Thu, Jul 25, 2024 at 03:44:54PM +0200, Ian Dannapel wrote: > > Hi Yilun, thanks for the review. > > > > Am Fr., 12. Juli 2024 um 09:00 Uhr schrieb Xu Yilun <yilun.xu@linux.intel.com>: > > > > > > On Fri, Jun 28, 2024 at 05:23:46PM +0200, iansdannapel@gmail.com wrote: > > > > From: Ian Dannapel <iansdannapel@gmail.com> > > > > > > > > > > Please don't reply to the previous series when you post a new version. > > sure > > > > > > > Add a new driver for loading binary firmware using "SPI passive > > > > > > Loading to some nvram or reporgraming to FPGA logic blocks. > > Sorry for typo, this is a question: > > Loading to some nvram or reporgraming to FPGA logic blocks? The datasheet refers to it as configuration RAM (CRAM) and must be loaded on every boot up. > > > > > > > > programming" on Efinix FPGAs. > > > > > > > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com> > > > > --- > > > > drivers/fpga/Kconfig | 8 + > > > > drivers/fpga/Makefile | 1 + > > > > drivers/fpga/efinix-trion-spi-passive.c | 219 ++++++++++++++++++++++++ > > > > 3 files changed, 228 insertions(+) > > > > create mode 100644 drivers/fpga/efinix-trion-spi-passive.c > > > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > > > > index 37b35f58f0df..25579510e49e 100644 > > > > --- a/drivers/fpga/Kconfig > > > > +++ b/drivers/fpga/Kconfig > > > > @@ -83,6 +83,14 @@ config FPGA_MGR_XILINX_SPI > > > > FPGA manager driver support for Xilinx FPGA configuration > > > > over slave serial interface. > > > > > > > > +config FPGA_MGR_EFINIX_SPI > > > > + tristate "Efinix FPGA configuration over SPI passive" > > > > + depends on SPI > > > > + help > > > > + This option enables support for the FPGA manager driver to > > > > + configure Efinix Trion and Titanium Series FPGAs over SPI > > > > + using passive serial mode. > > > > + > > > > config FPGA_MGR_ICE40_SPI > > > > tristate "Lattice iCE40 SPI" > > > > depends on OF && SPI > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > > > > index aeb89bb13517..1a95124ff847 100644 > > > > --- a/drivers/fpga/Makefile > > > > +++ b/drivers/fpga/Makefile > > > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > > > > obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o > > > > obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o > > > > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > > > > +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-trion-spi-passive.o > > > > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > > > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o > > > > obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o > > > > diff --git a/drivers/fpga/efinix-trion-spi-passive.c b/drivers/fpga/efinix-trion-spi-passive.c > > > > new file mode 100644 > > > > index 000000000000..eb2592e788b9 > > > > --- /dev/null > > > > +++ b/drivers/fpga/efinix-trion-spi-passive.c > > > > @@ -0,0 +1,219 @@ > > > > +// SPDX-License-Identifier: GPL-2.0-only > > > > +/* > > > > + * Trion and Titanium Series FPGA SPI Passive Programming Driver > > > > + * > > > > + * Copyright (C) 2024 iris-GmbH infrared & intelligent sensors > > > > + * > > > > + * Ian Dannapel <iansdannapel@gmail.com> > > > > + * > > > > + * Manage Efinix FPGA firmware that is loaded over SPI using > > > > + * the serial configuration interface. > > > > + */ > > > > + > > > > +#include <linux/delay.h> > > > > +#include <linux/device.h> > > > > +#include <linux/fpga/fpga-mgr.h> > > > > +#include <linux/gpio/consumer.h> > > > > +#include <linux/module.h> > > > > +#include <linux/mod_devicetable.h> > > > > +#include <linux/of.h> > > > > +#include <linux/spi/spi.h> > > > > +#include <linux/sizes.h> > > > > + > > > > +struct efinix_spi_conf { > > > > + struct spi_device *spi; > > > > + struct gpio_desc *cdone; > > > > + struct gpio_desc *creset; > > > > + struct gpio_desc *cs; > > > > +}; > > > > + > > > > +static int get_cdone_gpio(struct fpga_manager *mgr) > > > > > > Is it better use 'struct efinix_spi_conf *conf' as parameter? > > > > > > Same for the following functions. > > > > > > > +{ > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > + int ret; > > > > + > > > > + ret = gpiod_get_value(conf->cdone); > > > > + if (ret < 0) > > > > + dev_err(&mgr->dev, "Error reading CDONE (%d)\n", ret); > > > > + > > > > + return ret; > > > > +} > > > > + > > > > +static void reset(struct fpga_manager *mgr) > > > > > > Please unify the naming of the internal functions. You use > > > 'efinix_spi_apply_clk_cycles()' below. > > > > > > > +{ > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > + > > > > + gpiod_set_value(conf->creset, 1); > > > > + /* wait tCRESET_N */ > > > > + usleep_range(5, 15); > > > > + gpiod_set_value(conf->creset, 0); > > > > +} > > > > + > > > > +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) > > > > +{ > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > + > > > > + if (conf->cdone && get_cdone_gpio(mgr) == 1) > > > > + return FPGA_MGR_STATE_OPERATING; > > > > + > > > > + return FPGA_MGR_STATE_UNKNOWN; > > > > +} > > > > + > > > > +static int efinix_spi_apply_clk_cycles(struct fpga_manager *mgr) > > > > +{ > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > + char data[13] = {0}; > > > > + > > > > + return spi_write(conf->spi, data, sizeof(data)); > > > > +} > > > > + > > > > +static int efinix_spi_write_init(struct fpga_manager *mgr, > > > > + struct fpga_image_info *info, > > > > + const char *buf, size_t count) > > > > +{ > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > + > > > > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > > > > + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); > > > > + return -EINVAL; > > > > + } > > > > + > > > > + /* reset with chip select active */ > > > > + gpiod_set_value(conf->cs, 1); > > > > > > Why operating chip selective at SPI client driver? Isn't it the job for SPI > > > controller? > > to enter the passive programming mode, a reset must be executed while > > the chip select is active. > > The is controlling the chip select from here, since I expect that the > > SPI controller to only activate > > the CS when communicating. > > The concern is, it may conflict with the underlying cs control in spi > controller. > > There are several control flags in struct spi_transfter to affect cs. Is > there any chance using them, or try to improve if they doesn't meet your > request? The main problem of this chip is that probably the of SPI is out of spec, so would like to avoid changes in the spi contoller for this edge case. That is probably one the reasons that the datasheet does not recommend other devices on the same SPI bus. > > > > > > > > + usleep_range(5, 15); > > > > + reset(mgr); > > > > + > > > > + /* wait tDMIN */ > > > > + usleep_range(100, 150); > > And these ones, or you could use some delay controls in struct spi_transfer. I don't think spi_transfer delay option could work in this case, the data transfer did not start yet. > > > > > + > > > > + return 0; > > > > +} > > > > + > > > > +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf, > > > > + size_t count) > > > > +{ > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > + int ret; > > > > + > > > > + ret = spi_write(conf->spi, buf, count); > > > > + if (ret) { > > > > + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", > > > > + ret); > > > > + return ret; > > > > + } > > > > + > > > > + /* append at least 100 clock cycles */ > > > > + efinix_spi_apply_clk_cycles(mgr); > > > > + > > > > + /* release chip select */ > > > > + gpiod_set_value(conf->cs, 0); > > > > > > Is it correct? What if there is remaining data to write? > > I assumed that the spi controller should write complete buffer and > > decide on the transfer block size, > > so there shouldn't be any remaining data. Can someone confirm? > > This is not about spi transfer, it is the fpga_manager_ops.write could > be called multiple times during one time reprogramming. Please > investigate more about the FPGA mgr core. I see, I should move this to write_complete since the CS must stay low throughout the configuration. That is also a reason to avoid letting the SPI controller manage the CS gpio. > > Thanks, > Yilun Thanks Ian
On Sun, Jul 28, 2024 at 01:44:03PM +0200, Ian Dannapel wrote: > Am Sa., 27. Juli 2024 um 18:00 Uhr schrieb Xu Yilun <yilun.xu@linux.intel.com>: > > > > On Thu, Jul 25, 2024 at 03:44:54PM +0200, Ian Dannapel wrote: > > > Hi Yilun, thanks for the review. > > > > > > Am Fr., 12. Juli 2024 um 09:00 Uhr schrieb Xu Yilun <yilun.xu@linux.intel.com>: > > > > > > > > On Fri, Jun 28, 2024 at 05:23:46PM +0200, iansdannapel@gmail.com wrote: > > > > > From: Ian Dannapel <iansdannapel@gmail.com> > > > > > > > > > > > > > Please don't reply to the previous series when you post a new version. > > > sure > > > > > > > > > Add a new driver for loading binary firmware using "SPI passive > > > > > > > > Loading to some nvram or reporgraming to FPGA logic blocks. > > > > Sorry for typo, this is a question: > > > > Loading to some nvram or reporgraming to FPGA logic blocks? > The datasheet refers to it as configuration RAM (CRAM) and must be > loaded on every boot up. The FPGA reprogramming is about loading the FPGA logic blocks, and from the POV of the System, it is about runtime changing the HW and re-enumerate the devices. But some submitted fpga-mgr drivers are just used to to write nvram backend for FPGA, don't affect any running device at all. I think these drivers virtually have nothing to do with fpga-mgr. Some generic storage (e.g. nvram, mtd) or firmware image loading interfaces better fit them. I assume this driver is also of this kind. > > > > > > > > > > > programming" on Efinix FPGAs. > > > > > > > > > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com> > > > > > --- > > > > > drivers/fpga/Kconfig | 8 + > > > > > drivers/fpga/Makefile | 1 + > > > > > drivers/fpga/efinix-trion-spi-passive.c | 219 ++++++++++++++++++++++++ > > > > > 3 files changed, 228 insertions(+) > > > > > create mode 100644 drivers/fpga/efinix-trion-spi-passive.c > > > > > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > > > > > index 37b35f58f0df..25579510e49e 100644 > > > > > --- a/drivers/fpga/Kconfig > > > > > +++ b/drivers/fpga/Kconfig > > > > > @@ -83,6 +83,14 @@ config FPGA_MGR_XILINX_SPI > > > > > FPGA manager driver support for Xilinx FPGA configuration > > > > > over slave serial interface. > > > > > > > > > > +config FPGA_MGR_EFINIX_SPI > > > > > + tristate "Efinix FPGA configuration over SPI passive" > > > > > + depends on SPI > > > > > + help > > > > > + This option enables support for the FPGA manager driver to > > > > > + configure Efinix Trion and Titanium Series FPGAs over SPI > > > > > + using passive serial mode. > > > > > + > > > > > config FPGA_MGR_ICE40_SPI > > > > > tristate "Lattice iCE40 SPI" > > > > > depends on OF && SPI > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > > > > > index aeb89bb13517..1a95124ff847 100644 > > > > > --- a/drivers/fpga/Makefile > > > > > +++ b/drivers/fpga/Makefile > > > > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > > > > > obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o > > > > > obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o > > > > > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > > > > > +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-trion-spi-passive.o > > > > > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > > > > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o > > > > > obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o > > > > > diff --git a/drivers/fpga/efinix-trion-spi-passive.c b/drivers/fpga/efinix-trion-spi-passive.c > > > > > new file mode 100644 > > > > > index 000000000000..eb2592e788b9 > > > > > --- /dev/null > > > > > +++ b/drivers/fpga/efinix-trion-spi-passive.c > > > > > @@ -0,0 +1,219 @@ > > > > > +// SPDX-License-Identifier: GPL-2.0-only > > > > > +/* > > > > > + * Trion and Titanium Series FPGA SPI Passive Programming Driver > > > > > + * > > > > > + * Copyright (C) 2024 iris-GmbH infrared & intelligent sensors > > > > > + * > > > > > + * Ian Dannapel <iansdannapel@gmail.com> > > > > > + * > > > > > + * Manage Efinix FPGA firmware that is loaded over SPI using > > > > > + * the serial configuration interface. > > > > > + */ > > > > > + > > > > > +#include <linux/delay.h> > > > > > +#include <linux/device.h> > > > > > +#include <linux/fpga/fpga-mgr.h> > > > > > +#include <linux/gpio/consumer.h> > > > > > +#include <linux/module.h> > > > > > +#include <linux/mod_devicetable.h> > > > > > +#include <linux/of.h> > > > > > +#include <linux/spi/spi.h> > > > > > +#include <linux/sizes.h> > > > > > + > > > > > +struct efinix_spi_conf { > > > > > + struct spi_device *spi; > > > > > + struct gpio_desc *cdone; > > > > > + struct gpio_desc *creset; > > > > > + struct gpio_desc *cs; > > > > > +}; > > > > > + > > > > > +static int get_cdone_gpio(struct fpga_manager *mgr) > > > > > > > > Is it better use 'struct efinix_spi_conf *conf' as parameter? > > > > > > > > Same for the following functions. > > > > > > > > > +{ > > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > > + int ret; > > > > > + > > > > > + ret = gpiod_get_value(conf->cdone); > > > > > + if (ret < 0) > > > > > + dev_err(&mgr->dev, "Error reading CDONE (%d)\n", ret); > > > > > + > > > > > + return ret; > > > > > +} > > > > > + > > > > > +static void reset(struct fpga_manager *mgr) > > > > > > > > Please unify the naming of the internal functions. You use > > > > 'efinix_spi_apply_clk_cycles()' below. > > > > > > > > > +{ > > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > > + > > > > > + gpiod_set_value(conf->creset, 1); > > > > > + /* wait tCRESET_N */ > > > > > + usleep_range(5, 15); > > > > > + gpiod_set_value(conf->creset, 0); > > > > > +} > > > > > + > > > > > +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) > > > > > +{ > > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > > + > > > > > + if (conf->cdone && get_cdone_gpio(mgr) == 1) > > > > > + return FPGA_MGR_STATE_OPERATING; > > > > > + > > > > > + return FPGA_MGR_STATE_UNKNOWN; > > > > > +} > > > > > + > > > > > +static int efinix_spi_apply_clk_cycles(struct fpga_manager *mgr) > > > > > +{ > > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > > + char data[13] = {0}; > > > > > + > > > > > + return spi_write(conf->spi, data, sizeof(data)); > > > > > +} > > > > > + > > > > > +static int efinix_spi_write_init(struct fpga_manager *mgr, > > > > > + struct fpga_image_info *info, > > > > > + const char *buf, size_t count) > > > > > +{ > > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > > + > > > > > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > > > > > + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); > > > > > + return -EINVAL; > > > > > + } > > > > > + > > > > > + /* reset with chip select active */ > > > > > + gpiod_set_value(conf->cs, 1); > > > > > > > > Why operating chip selective at SPI client driver? Isn't it the job for SPI > > > > controller? > > > to enter the passive programming mode, a reset must be executed while > > > the chip select is active. > > > The is controlling the chip select from here, since I expect that the > > > SPI controller to only activate > > > the CS when communicating. > > > > The concern is, it may conflict with the underlying cs control in spi > > controller. > > > > There are several control flags in struct spi_transfter to affect cs. Is > > there any chance using them, or try to improve if they doesn't meet your > > request? > The main problem of this chip is that probably the of SPI is out of > spec, so would like to avoid changes in the spi contoller for this > edge case. > That is probably one the reasons that the datasheet does not recommend > other devices on the same SPI bus. I think anyway you need to communicate with spi controller driver and have one voice how/who to take control of cs, rather than blindly operate at both sides. Thanks, Yilun
Am Mo., 29. Juli 2024 um 16:52 Uhr schrieb Xu Yilun <yilun.xu@linux.intel.com>: > > On Sun, Jul 28, 2024 at 01:44:03PM +0200, Ian Dannapel wrote: > > Am Sa., 27. Juli 2024 um 18:00 Uhr schrieb Xu Yilun <yilun.xu@linux.intel.com>: > > > > > > On Thu, Jul 25, 2024 at 03:44:54PM +0200, Ian Dannapel wrote: > > > > Hi Yilun, thanks for the review. > > > > > > > > Am Fr., 12. Juli 2024 um 09:00 Uhr schrieb Xu Yilun <yilun.xu@linux.intel.com>: > > > > > > > > > > On Fri, Jun 28, 2024 at 05:23:46PM +0200, iansdannapel@gmail.com wrote: > > > > > > From: Ian Dannapel <iansdannapel@gmail.com> > > > > > > > > > > > > > > > > Please don't reply to the previous series when you post a new version. > > > > sure > > > > > > > > > > > Add a new driver for loading binary firmware using "SPI passive > > > > > > > > > > Loading to some nvram or reporgraming to FPGA logic blocks. > > > > > > Sorry for typo, this is a question: > > > > > > Loading to some nvram or reporgraming to FPGA logic blocks? > > The datasheet refers to it as configuration RAM (CRAM) and must be > > loaded on every boot up. > > The FPGA reprogramming is about loading the FPGA logic blocks, and from > the POV of the System, it is about runtime changing the HW and > re-enumerate the devices. > > But some submitted fpga-mgr drivers are just used to to write nvram > backend for FPGA, don't affect any running device at all. I think these > drivers virtually have nothing to do with fpga-mgr. Some generic > storage (e.g. nvram, mtd) or firmware image loading interfaces better > fit them. I assume this driver is also of this kind. To clarify, this driver does not write to a nvram or any persistent memory. Programming or reprogramming at runtime is necessary, but partial reprogramming is not supported. > > > > > > > > > > > > > > > programming" on Efinix FPGAs. > > > > > > > > > > > > Signed-off-by: Ian Dannapel <iansdannapel@gmail.com> > > > > > > --- > > > > > > drivers/fpga/Kconfig | 8 + > > > > > > drivers/fpga/Makefile | 1 + > > > > > > drivers/fpga/efinix-trion-spi-passive.c | 219 ++++++++++++++++++++++++ > > > > > > 3 files changed, 228 insertions(+) > > > > > > create mode 100644 drivers/fpga/efinix-trion-spi-passive.c > > > > > > > > > > > > diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig > > > > > > index 37b35f58f0df..25579510e49e 100644 > > > > > > --- a/drivers/fpga/Kconfig > > > > > > +++ b/drivers/fpga/Kconfig > > > > > > @@ -83,6 +83,14 @@ config FPGA_MGR_XILINX_SPI > > > > > > FPGA manager driver support for Xilinx FPGA configuration > > > > > > over slave serial interface. > > > > > > > > > > > > +config FPGA_MGR_EFINIX_SPI > > > > > > + tristate "Efinix FPGA configuration over SPI passive" > > > > > > + depends on SPI > > > > > > + help > > > > > > + This option enables support for the FPGA manager driver to > > > > > > + configure Efinix Trion and Titanium Series FPGAs over SPI > > > > > > + using passive serial mode. > > > > > > + > > > > > > config FPGA_MGR_ICE40_SPI > > > > > > tristate "Lattice iCE40 SPI" > > > > > > depends on OF && SPI > > > > > > diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile > > > > > > index aeb89bb13517..1a95124ff847 100644 > > > > > > --- a/drivers/fpga/Makefile > > > > > > +++ b/drivers/fpga/Makefile > > > > > > @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o > > > > > > obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o > > > > > > obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o > > > > > > obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o > > > > > > +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-trion-spi-passive.o > > > > > > obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o > > > > > > obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o > > > > > > obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o > > > > > > diff --git a/drivers/fpga/efinix-trion-spi-passive.c b/drivers/fpga/efinix-trion-spi-passive.c > > > > > > new file mode 100644 > > > > > > index 000000000000..eb2592e788b9 > > > > > > --- /dev/null > > > > > > +++ b/drivers/fpga/efinix-trion-spi-passive.c > > > > > > @@ -0,0 +1,219 @@ > > > > > > +// SPDX-License-Identifier: GPL-2.0-only > > > > > > +/* > > > > > > + * Trion and Titanium Series FPGA SPI Passive Programming Driver > > > > > > + * > > > > > > + * Copyright (C) 2024 iris-GmbH infrared & intelligent sensors > > > > > > + * > > > > > > + * Ian Dannapel <iansdannapel@gmail.com> > > > > > > + * > > > > > > + * Manage Efinix FPGA firmware that is loaded over SPI using > > > > > > + * the serial configuration interface. > > > > > > + */ > > > > > > + > > > > > > +#include <linux/delay.h> > > > > > > +#include <linux/device.h> > > > > > > +#include <linux/fpga/fpga-mgr.h> > > > > > > +#include <linux/gpio/consumer.h> > > > > > > +#include <linux/module.h> > > > > > > +#include <linux/mod_devicetable.h> > > > > > > +#include <linux/of.h> > > > > > > +#include <linux/spi/spi.h> > > > > > > +#include <linux/sizes.h> > > > > > > + > > > > > > +struct efinix_spi_conf { > > > > > > + struct spi_device *spi; > > > > > > + struct gpio_desc *cdone; > > > > > > + struct gpio_desc *creset; > > > > > > + struct gpio_desc *cs; > > > > > > +}; > > > > > > + > > > > > > +static int get_cdone_gpio(struct fpga_manager *mgr) > > > > > > > > > > Is it better use 'struct efinix_spi_conf *conf' as parameter? > > > > > > > > > > Same for the following functions. > > > > > > > > > > > +{ > > > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > > > + int ret; > > > > > > + > > > > > > + ret = gpiod_get_value(conf->cdone); > > > > > > + if (ret < 0) > > > > > > + dev_err(&mgr->dev, "Error reading CDONE (%d)\n", ret); > > > > > > + > > > > > > + return ret; > > > > > > +} > > > > > > + > > > > > > +static void reset(struct fpga_manager *mgr) > > > > > > > > > > Please unify the naming of the internal functions. You use > > > > > 'efinix_spi_apply_clk_cycles()' below. > > > > > > > > > > > +{ > > > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > > > + > > > > > > + gpiod_set_value(conf->creset, 1); > > > > > > + /* wait tCRESET_N */ > > > > > > + usleep_range(5, 15); > > > > > > + gpiod_set_value(conf->creset, 0); > > > > > > +} > > > > > > + > > > > > > +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) > > > > > > +{ > > > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > > > + > > > > > > + if (conf->cdone && get_cdone_gpio(mgr) == 1) > > > > > > + return FPGA_MGR_STATE_OPERATING; > > > > > > + > > > > > > + return FPGA_MGR_STATE_UNKNOWN; > > > > > > +} > > > > > > + > > > > > > +static int efinix_spi_apply_clk_cycles(struct fpga_manager *mgr) > > > > > > +{ > > > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > > > + char data[13] = {0}; > > > > > > + > > > > > > + return spi_write(conf->spi, data, sizeof(data)); > > > > > > +} > > > > > > + > > > > > > +static int efinix_spi_write_init(struct fpga_manager *mgr, > > > > > > + struct fpga_image_info *info, > > > > > > + const char *buf, size_t count) > > > > > > +{ > > > > > > + struct efinix_spi_conf *conf = mgr->priv; > > > > > > + > > > > > > + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { > > > > > > + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); > > > > > > + return -EINVAL; > > > > > > + } > > > > > > + > > > > > > + /* reset with chip select active */ > > > > > > + gpiod_set_value(conf->cs, 1); > > > > > > > > > > Why operating chip selective at SPI client driver? Isn't it the job for SPI > > > > > controller? > > > > to enter the passive programming mode, a reset must be executed while > > > > the chip select is active. > > > > The is controlling the chip select from here, since I expect that the > > > > SPI controller to only activate > > > > the CS when communicating. > > > > > > The concern is, it may conflict with the underlying cs control in spi > > > controller. > > > > > > There are several control flags in struct spi_transfter to affect cs. Is > > > there any chance using them, or try to improve if they doesn't meet your > > > request? > > The main problem of this chip is that probably the of SPI is out of > > spec, so would like to avoid changes in the spi contoller for this > > edge case. > > That is probably one the reasons that the datasheet does not recommend > > other devices on the same SPI bus. > > I think anyway you need to communicate with spi controller driver and > have one voice how/who to take control of cs, rather than blindly > operate at both sides. I did not find a clear solution yet. This FGPA device requires an SPI without a chip-select signal and no other device transaction should be allowed in between reprogramming, which seems to be a very specific case for the SPI Controller to manage > > Thanks, > Yilun Thank Ian
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig index 37b35f58f0df..25579510e49e 100644 --- a/drivers/fpga/Kconfig +++ b/drivers/fpga/Kconfig @@ -83,6 +83,14 @@ config FPGA_MGR_XILINX_SPI FPGA manager driver support for Xilinx FPGA configuration over slave serial interface. +config FPGA_MGR_EFINIX_SPI + tristate "Efinix FPGA configuration over SPI passive" + depends on SPI + help + This option enables support for the FPGA manager driver to + configure Efinix Trion and Titanium Series FPGAs over SPI + using passive serial mode. + config FPGA_MGR_ICE40_SPI tristate "Lattice iCE40 SPI" depends on OF && SPI diff --git a/drivers/fpga/Makefile b/drivers/fpga/Makefile index aeb89bb13517..1a95124ff847 100644 --- a/drivers/fpga/Makefile +++ b/drivers/fpga/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_FPGA_MGR_TS73XX) += ts73xx-fpga.o obj-$(CONFIG_FPGA_MGR_XILINX_CORE) += xilinx-core.o obj-$(CONFIG_FPGA_MGR_XILINX_SELECTMAP) += xilinx-selectmap.o obj-$(CONFIG_FPGA_MGR_XILINX_SPI) += xilinx-spi.o +obj-$(CONFIG_FPGA_MGR_EFINIX_SPI) += efinix-trion-spi-passive.o obj-$(CONFIG_FPGA_MGR_ZYNQ_FPGA) += zynq-fpga.o obj-$(CONFIG_FPGA_MGR_ZYNQMP_FPGA) += zynqmp-fpga.o obj-$(CONFIG_FPGA_MGR_VERSAL_FPGA) += versal-fpga.o diff --git a/drivers/fpga/efinix-trion-spi-passive.c b/drivers/fpga/efinix-trion-spi-passive.c new file mode 100644 index 000000000000..eb2592e788b9 --- /dev/null +++ b/drivers/fpga/efinix-trion-spi-passive.c @@ -0,0 +1,219 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Trion and Titanium Series FPGA SPI Passive Programming Driver + * + * Copyright (C) 2024 iris-GmbH infrared & intelligent sensors + * + * Ian Dannapel <iansdannapel@gmail.com> + * + * Manage Efinix FPGA firmware that is loaded over SPI using + * the serial configuration interface. + */ + +#include <linux/delay.h> +#include <linux/device.h> +#include <linux/fpga/fpga-mgr.h> +#include <linux/gpio/consumer.h> +#include <linux/module.h> +#include <linux/mod_devicetable.h> +#include <linux/of.h> +#include <linux/spi/spi.h> +#include <linux/sizes.h> + +struct efinix_spi_conf { + struct spi_device *spi; + struct gpio_desc *cdone; + struct gpio_desc *creset; + struct gpio_desc *cs; +}; + +static int get_cdone_gpio(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf = mgr->priv; + int ret; + + ret = gpiod_get_value(conf->cdone); + if (ret < 0) + dev_err(&mgr->dev, "Error reading CDONE (%d)\n", ret); + + return ret; +} + +static void reset(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf = mgr->priv; + + gpiod_set_value(conf->creset, 1); + /* wait tCRESET_N */ + usleep_range(5, 15); + gpiod_set_value(conf->creset, 0); +} + +static enum fpga_mgr_states efinix_spi_state(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf = mgr->priv; + + if (conf->cdone && get_cdone_gpio(mgr) == 1) + return FPGA_MGR_STATE_OPERATING; + + return FPGA_MGR_STATE_UNKNOWN; +} + +static int efinix_spi_apply_clk_cycles(struct fpga_manager *mgr) +{ + struct efinix_spi_conf *conf = mgr->priv; + char data[13] = {0}; + + return spi_write(conf->spi, data, sizeof(data)); +} + +static int efinix_spi_write_init(struct fpga_manager *mgr, + struct fpga_image_info *info, + const char *buf, size_t count) +{ + struct efinix_spi_conf *conf = mgr->priv; + + if (info->flags & FPGA_MGR_PARTIAL_RECONFIG) { + dev_err(&mgr->dev, "Partial reconfiguration not supported\n"); + return -EINVAL; + } + + /* reset with chip select active */ + gpiod_set_value(conf->cs, 1); + usleep_range(5, 15); + reset(mgr); + + /* wait tDMIN */ + usleep_range(100, 150); + + return 0; +} + +static int efinix_spi_write(struct fpga_manager *mgr, const char *buf, + size_t count) +{ + struct efinix_spi_conf *conf = mgr->priv; + int ret; + + ret = spi_write(conf->spi, buf, count); + if (ret) { + dev_err(&mgr->dev, "SPI error in firmware write: %d\n", + ret); + return ret; + } + + /* append at least 100 clock cycles */ + efinix_spi_apply_clk_cycles(mgr); + + /* release chip select */ + gpiod_set_value(conf->cs, 0); + + return 0; +} + +static int efinix_spi_write_complete(struct fpga_manager *mgr, + struct fpga_image_info *info) +{ + struct efinix_spi_conf *conf = mgr->priv; + unsigned long timeout = + jiffies + usecs_to_jiffies(info->config_complete_timeout_us); + bool expired = false; + int done; + + if (conf->cdone) { + while (!expired) { + expired = time_after(jiffies, timeout); + + done = get_cdone_gpio(mgr); + if (done < 0) + return done; + + if (done) + break; + } + } + + if (expired) + return -ETIMEDOUT; + + /* wait tUSER */ + usleep_range(75, 125); + + return 0; +} + +static const struct fpga_manager_ops efinix_spi_ops = { + .state = efinix_spi_state, + .write_init = efinix_spi_write_init, + .write = efinix_spi_write, + .write_complete = efinix_spi_write_complete, +}; + +static int efinix_spi_probe(struct spi_device *spi) +{ + struct efinix_spi_conf *conf; + struct fpga_manager *mgr; + + conf = devm_kzalloc(&spi->dev, sizeof(*conf), GFP_KERNEL); + if (!conf) + return -ENOMEM; + + conf->spi = spi; + + conf->creset = devm_gpiod_get(&spi->dev, "creset", GPIOD_OUT_HIGH); + if (IS_ERR(conf->creset)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->creset), + "Failed to get RESET gpio\n"); + + conf->cs = devm_gpiod_get(&spi->dev, "cs", GPIOD_OUT_HIGH); + if (IS_ERR(conf->cs)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->cs), + "Failed to get CHIP_SELECT gpio\n"); + + if (!(spi->mode & SPI_CPHA) || !(spi->mode & SPI_CPOL)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->cs), + "Unsupported SPI mode, set CPHA and CPOL\n"); + + conf->cdone = devm_gpiod_get_optional(&spi->dev, "cdone", GPIOD_IN); + if (IS_ERR(conf->cdone)) + return dev_err_probe(&spi->dev, PTR_ERR(conf->cdone), + "Failed to get CDONE gpio\n"); + + mgr = devm_fpga_mgr_register(&spi->dev, + "Efinix SPI Passive Programming FPGA Manager", + &efinix_spi_ops, conf); + + return PTR_ERR_OR_ZERO(mgr); +} + +#ifdef CONFIG_OF +static const struct of_device_id efnx_spi_of_match[] = { + { .compatible = "efinix,trion-spi-passive", }, + { .compatible = "efinix,titanium-spi-passive", }, + {} +}; +MODULE_DEVICE_TABLE(of, efnx_spi_of_match); +#endif + +static const struct spi_device_id efinix_ids[] = { + { "trion-spi-passive", 0 }, + { "titanium-spi-passive", 0 }, + {}, +}; +MODULE_DEVICE_TABLE(spi, efinix_ids); + + +static struct spi_driver efinix_spi_passive_driver = { + .driver = { + .name = "efinix-fpga-spi-passive", + .of_match_table = of_match_ptr(efnx_spi_of_match), + }, + .probe = efinix_spi_probe, + .id_table = efinix_ids, +}; + +module_spi_driver(efinix_spi_passive_driver); + +MODULE_LICENSE("GPL"); +MODULE_AUTHOR("Ian Dannapel <iansdannapel@gmail.com>"); +MODULE_DESCRIPTION("Load Efinix FPGA firmware over SPI passive");