[v4,0/4] Add board support for Sipeed LicheeRV Nano

Message

Thomas Bonnefille July 11, 2024, 10:01 a.m. UTC

The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
minimal device tree files for this board to make it boot to a basic
shell.

Signed-off-by: Thomas Bonnefille <[e-mail]>
---
Changes in v4:
- Add correct bindings configuration for SG2002 sdhci
- Drop commit "dt-bindings: timer: Add SOPHGO SG2002 clint" because it
  has already been merged in Daniel Lezcano git tree.
- Link to v3: https://lore.kernel.org/r/[e-mail]

Changes in v3:
- Remove /dts-v1/ directive from sg2002.dtsi file
- Add disable-wp property to sdhci node to avoid having a write
  protected SD card
- Drop changes in cv18xx.dtsi and cv1800b.dtsi
- Add fallback compatible to cv1800b in SDHCI node of sg2002.dtsi
- Link to v2: https://lore.kernel.org/r/[e-mail]

Changes in v2:
- Add SDHCI support
- Change device tree name to match the Makefile
- Add oscillator frequency
- Add aliases to other UARTs
- Add aliases to GPIOs
- Move compatible for SDHCI from common DT to specific DT 
- Link to v1: https://lore.kernel.org/r/[e-mail]

---
Thomas Bonnefille (4):
      dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
      dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
      riscv: dts: sophgo: Add initial SG2002 SoC device tree
      riscv: dts: sophgo: Add LicheeRV Nano board device tree

 .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
 .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
 arch/riscv/boot/dts/sophgo/Makefile                |  1 +
 .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
 arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
 5 files changed, 93 insertions(+)
---
base-commit: d20f6b3d747c36889b7ce75ee369182af3decb6b
change-id: 20240515-sg2002-93dce1d263be

Best regards,

Comments

Inochi Amaoto July 12, 2024, 12:31 a.m. UTC | #1

On Thu, Jul 11, 2024 at 12:01:27PM GMT, Thomas Bonnefille wrote:
> The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
> minimal device tree files for this board to make it boot to a basic
> shell.
> 
> Signed-off-by: Thomas Bonnefille <[e-mail]>

Reviewed-by: Inochi Amaoto <[e-mail]>

> ---
> Changes in v4:
> - Add correct bindings configuration for SG2002 sdhci
> - Drop commit "dt-bindings: timer: Add SOPHGO SG2002 clint" because it
>   has already been merged in Daniel Lezcano git tree.
> - Link to v3: https://lore.kernel.org/r/[e-mail]
> 
> Changes in v3:
> - Remove /dts-v1/ directive from sg2002.dtsi file
> - Add disable-wp property to sdhci node to avoid having a write
>   protected SD card
> - Drop changes in cv18xx.dtsi and cv1800b.dtsi
> - Add fallback compatible to cv1800b in SDHCI node of sg2002.dtsi
> - Link to v2: https://lore.kernel.org/r/[e-mail]
> 
> Changes in v2:
> - Add SDHCI support
> - Change device tree name to match the Makefile
> - Add oscillator frequency
> - Add aliases to other UARTs
> - Add aliases to GPIOs
> - Move compatible for SDHCI from common DT to specific DT 
> - Link to v1: https://lore.kernel.org/r/[e-mail]
> 
> ---
> Thomas Bonnefille (4):
>       dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
>       dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
>       riscv: dts: sophgo: Add initial SG2002 SoC device tree
>       riscv: dts: sophgo: Add LicheeRV Nano board device tree
> 
>  .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
>  .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
>  arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>  .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
>  arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
>  5 files changed, 93 insertions(+)
> ---
> base-commit: d20f6b3d747c36889b7ce75ee369182af3decb6b
> change-id: 20240515-sg2002-93dce1d263be
> 
> Best regards,
> -- 
> Thomas Bonnefille <[e-mail]>
>

Chen Wang July 12, 2024, 1:27 a.m. UTC | #2

On 2024/7/11 18:01, Thomas Bonnefille wrote:
> The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
> minimal device tree files for this board to make it boot to a basic
> shell.
>
> Signed-off-by: Thomas Bonnefille <[e-mail]>
> ---
> Changes in v4:
> - Add correct bindings configuration for SG2002 sdhci
> - Drop commit "dt-bindings: timer: Add SOPHGO SG2002 clint" because it
>    has already been merged in Daniel Lezcano git tree.
> - Link to v3: https://lore.kernel.org/r/[e-mail]
>
> Changes in v3:
> - Remove /dts-v1/ directive from sg2002.dtsi file
> - Add disable-wp property to sdhci node to avoid having a write
>    protected SD card
> - Drop changes in cv18xx.dtsi and cv1800b.dtsi
> - Add fallback compatible to cv1800b in SDHCI node of sg2002.dtsi
> - Link to v2: https://lore.kernel.org/r/[e-mail]
>
> Changes in v2:
> - Add SDHCI support
> - Change device tree name to match the Makefile
> - Add oscillator frequency
> - Add aliases to other UARTs
> - Add aliases to GPIOs
> - Move compatible for SDHCI from common DT to specific DT
> - Link to v1: https://lore.kernel.org/r/[e-mail]
>
> ---
> Thomas Bonnefille (4):
>        dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
>        dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
>        riscv: dts: sophgo: Add initial SG2002 SoC device tree
>        riscv: dts: sophgo: Add LicheeRV Nano board device tree
>
>   .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
>   .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
>   arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>   .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
>   arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
>   5 files changed, 93 insertions(+)
> ---
> base-commit: d20f6b3d747c36889b7ce75ee369182af3decb6b
> change-id: 20240515-sg2002-93dce1d263be
>
> Best regards,
Hi, Thomas,

This stuff is already too late for 6.11 as I already sent my PRs. I will 
handle this next period.

Cheers,

Chen

Chen Wang July 12, 2024, 1:33 a.m. UTC | #3

hi, Conor,

How about letting me PR all the four patches in this patchset? Because 
they are all related to sophgo, it would be better to PR them together 
to avoid confusion.
Especially about the change of sifive,plic-1.0.0.yaml, my original 
understanding was that it should be handled by you.

Regards,

Chen

On 2024/7/11 18:01, Thomas Bonnefille wrote:
> The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
> minimal device tree files for this board to make it boot to a basic
> shell.
>
> Signed-off-by: Thomas Bonnefille <[e-mail]>
> ---
> Changes in v4:
> - Add correct bindings configuration for SG2002 sdhci
> - Drop commit "dt-bindings: timer: Add SOPHGO SG2002 clint" because it
>    has already been merged in Daniel Lezcano git tree.
> - Link to v3: https://lore.kernel.org/r/[e-mail]
>
> Changes in v3:
> - Remove /dts-v1/ directive from sg2002.dtsi file
> - Add disable-wp property to sdhci node to avoid having a write
>    protected SD card
> - Drop changes in cv18xx.dtsi and cv1800b.dtsi
> - Add fallback compatible to cv1800b in SDHCI node of sg2002.dtsi
> - Link to v2: https://lore.kernel.org/r/[e-mail]
>
> Changes in v2:
> - Add SDHCI support
> - Change device tree name to match the Makefile
> - Add oscillator frequency
> - Add aliases to other UARTs
> - Add aliases to GPIOs
> - Move compatible for SDHCI from common DT to specific DT
> - Link to v1: https://lore.kernel.org/r/[e-mail]
>
> ---
> Thomas Bonnefille (4):
>        dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
>        dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
>        riscv: dts: sophgo: Add initial SG2002 SoC device tree
>        riscv: dts: sophgo: Add LicheeRV Nano board device tree
>
>   .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
>   .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
>   arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>   .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
>   arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
>   5 files changed, 93 insertions(+)
> ---
> base-commit: d20f6b3d747c36889b7ce75ee369182af3decb6b
> change-id: 20240515-sg2002-93dce1d263be
>
> Best regards,

Conor Dooley July 12, 2024, 2:15 p.m. UTC | #4

On Fri, Jul 12, 2024 at 09:33:46AM +0800, Chen Wang wrote:
> >   .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
> >   .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
> >   arch/riscv/boot/dts/sophgo/Makefile                |  1 +
> >   .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
> >   arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
> >   5 files changed, 93 insertions(+)
> 
> How about letting me PR all the four patches in this patchset? Because they
> are all related to sophgo, it would be better to PR them together to avoid
> confusion.
> Especially about the change of sifive,plic-1.0.0.yaml, my original
> understanding was that it should be handled by you.

No, stuff like the plic should really be handled by Thomas as he is the
interrupt controller maintainer, not by me. Usually though, neither the
timer or interrupt controller maintainers seem to care about these sorts
of binding patches which is why they ended up going with the dts.
Ideally the plic patch would go through the tip tree, but I think
there's unlikely to be sleep lost over a trivial binding change going
with the dts user.

Chen Wang July 13, 2024, 12:13 a.m. UTC | #5

On 2024/7/12 22:15, Conor Dooley wrote:
> On Fri, Jul 12, 2024 at 09:33:46AM +0800, Chen Wang wrote:
>>>    .../interrupt-controller/sifive,plic-1.0.0.yaml    |  1 +
>>>    .../devicetree/bindings/riscv/sophgo.yaml          |  5 ++
>>>    arch/riscv/boot/dts/sophgo/Makefile                |  1 +
>>>    .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts     | 54 ++++++++++++++++++++++
>>>    arch/riscv/boot/dts/sophgo/sg2002.dtsi             | 32 +++++++++++++
>>>    5 files changed, 93 insertions(+)
>> How about letting me PR all the four patches in this patchset? Because they
>> are all related to sophgo, it would be better to PR them together to avoid
>> confusion.
>> Especially about the change of sifive,plic-1.0.0.yaml, my original
>> understanding was that it should be handled by you.
> No, stuff like the plic should really be handled by Thomas as he is the
> interrupt controller maintainer, not by me. Usually though, neither the
> timer or interrupt controller maintainers seem to care about these sorts
> of binding patches which is why they ended up going with the dts.
> Ideally the plic patch would go through the tip tree, but I think
> there's unlikely to be sleep lost over a trivial binding change going
> with the dts user.

Thank you Cornor for your input, I will handle these patches together 
with dts.

Regards,

Chen

Inochi Amaoto Aug. 26, 2024, 2:55 a.m. UTC | #6

On Thu, 11 Jul 2024 12:01:27 +0200, Thomas Bonnefille wrote:
> The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds
> minimal device tree files for this board to make it boot to a basic
> shell.
> 
> 

Applied to cv18xx/for-next, thanks!

[1/4] dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic
      https://github.com/sophgo/linux/commit/866e86d73f0a1bc4e482162276c4e9765597362c
[2/4] dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles
      https://github.com/sophgo/linux/commit/4ecff14f1a45f82c60ec77d2662e439d088fefd6
[3/4] riscv: dts: sophgo: Add initial SG2002 SoC device tree
      https://github.com/sophgo/linux/commit/05949703b659b138a9ade02e456ddfe112581457
[4/4] riscv: dts: sophgo: Add LicheeRV Nano board device tree
      https://github.com/sophgo/linux/commit/c919edd074714f53763cbfeb8bdc9f1accfa7f52

Thanks,
Inochi