| Message ID | 20240710132830.14710-3-didi.debian@cknow.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | sdmmc/sdio/emmc improvements for RK3328 | expand |
Hello Diederik, On 2024-07-10 15:28, Diederik de Haas wrote: > From: Alex Bee <knaerzche@gmail.com> > > RK3328 SoC has a fourth mmc controller called SDMMC_EXT. Some > boards have sdio wifi connected to it. In order to use it > one would have to add the pinctrls from sdmmc0ext group which > is done on board level. > > Signed-off-by: Alex Bee <knaerzche@gmail.com> > Signed-off-by: Diederik de Haas <didi.debian@cknow.org> Looking good to me, cross-referencing the RK3328 TRM and the downstream RK3328 SoC dtsi checks out. Though, it will remain inert in our codebase, because no supported boards use it, but that's fine, we're still improving the correctness of the RK3328 SoC dtsi. Reviewed-by: Dragan Simic <dsimic@manjaro.org> > --- > arch/arm64/boot/dts/rockchip/rk3328.dtsi | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi > b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > index b01efd6d042c..95c3f1303544 100644 > --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi > +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi > @@ -1036,6 +1036,20 @@ usb_host0_ohci: usb@ff5d0000 { > status = "disabled"; > }; > > + sdmmc_ext: mmc@ff5f0000 { > + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; > + reg = <0x0 0xff5f0000 0x0 0x4000>; > + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, > + <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; > + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; > + fifo-depth = <0x100>; > + max-frequency = <150000000>; > + resets = <&cru SRST_SDMMCEXT>; > + reset-names = "reset"; > + status = "disabled"; > + }; > + > usbdrd3: usb@ff600000 { > compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; > reg = <0x0 0xff600000 0x0 0x100000>;
Hi Dragan, Thanks for the reviews! On Saturday, 13 July 2024 15:45:12 CEST Dragan Simic wrote: > Looking good to me, cross-referencing the RK3328 TRM and the > downstream RK3328 SoC dtsi checks out. Though, it will remain inert > in our codebase, because no supported boards use it, but that's fine, > we're still improving the correctness of the RK3328 SoC dtsi. Indeed. But it's hard to argue with technically correct ;-) Cheers, Diederik
Am 13.07.24 um 16:35 schrieb Diederik de Haas: > Hi Dragan, > > Thanks for the reviews! > > On Saturday, 13 July 2024 15:45:12 CEST Dragan Simic wrote: >> Looking good to me, cross-referencing the RK3328 TRM and the >> downstream RK3328 SoC dtsi checks out. Though, it will remain inert >> in our codebase, because no supported boards use it, but that's fine, >> we're still improving the correctness of the RK3328 SoC dtsi. > Indeed. But it's hard to argue with technically correct ;-) FWIW: (upstream supported) ROC-RK3328-PC has sdio wifi connected to this controller. Alex > Cheers, > Diederik
Hello Alex, On 2024-07-13 16:56, Alex Bee wrote: > Am 13.07.24 um 16:35 schrieb Diederik de Haas: >> Hi Dragan, >> >> Thanks for the reviews! >> >> On Saturday, 13 July 2024 15:45:12 CEST Dragan Simic wrote: >>> Looking good to me, cross-referencing the RK3328 TRM and the >>> downstream RK3328 SoC dtsi checks out. Though, it will remain inert >>> in our codebase, because no supported boards use it, but that's fine, >>> we're still improving the correctness of the RK3328 SoC dtsi. >> Indeed. But it's hard to argue with technically correct ;-) > > FWIW: (upstream supported) ROC-RK3328-PC has sdio wifi connected to > this > controller. Oh, it does? Good to hear, so the additions to the RK3328 SoC dtsi shouldn't remain inert. :)
diff --git a/arch/arm64/boot/dts/rockchip/rk3328.dtsi b/arch/arm64/boot/dts/rockchip/rk3328.dtsi index b01efd6d042c..95c3f1303544 100644 --- a/arch/arm64/boot/dts/rockchip/rk3328.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3328.dtsi @@ -1036,6 +1036,20 @@ usb_host0_ohci: usb@ff5d0000 { status = "disabled"; }; + sdmmc_ext: mmc@ff5f0000 { + compatible = "rockchip,rk3328-dw-mshc", "rockchip,rk3288-dw-mshc"; + reg = <0x0 0xff5f0000 0x0 0x4000>; + interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cru HCLK_SDMMC_EXT>, <&cru SCLK_SDMMC_EXT>, + <&cru SCLK_SDMMC_EXT_DRV>, <&cru SCLK_SDMMC_EXT_SAMPLE>; + clock-names = "biu", "ciu", "ciu-drive", "ciu-sample"; + fifo-depth = <0x100>; + max-frequency = <150000000>; + resets = <&cru SRST_SDMMCEXT>; + reset-names = "reset"; + status = "disabled"; + }; + usbdrd3: usb@ff600000 { compatible = "rockchip,rk3328-dwc3", "snps,dwc3"; reg = <0x0 0xff600000 0x0 0x100000>;