| Message ID | 20240711-th1520-clk-v3-0-6ff17bb318fb@tenstorrent.com (mailing list archive) |
|---|---|
| Headers | show |
| Series | clk: thead: Add support for TH1520 AP_SUBSYS clock controller | expand |
Quoting Drew Fustini (2024-07-11 09:56:18) > This series adds support for the AP sub-system clock controller in the > T-Head TH1520 [1]. Yangtao Li originally submitted this series in May > 2023 [2]. Jisheng made additional improvements and then passed on the > work in progress to me. > > Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] > Link: https://lore.kernel.org/all/20230515054402.27633-1-frank.li@vivo.com/ [2] > > Changes in v3: > - dt-binding patch has been applied to clk-next by Stephen but I'm > keeping it in the series for completeness. > - move dt-bindings include after linux includes in driver > - change rate to u64 in th1520_pll_vco_recalc_rate() > - replace do_div() with normal division operation in both > th1520_pll_vco_recalc_rate() and th1520_pll_postdiv_recalc_rate() > - add static to ccu_mux structs: c910_i0_clk, c910_clk, uart_sclk This didn't happen, so I just did it myself.
This series adds support for the AP sub-system clock controller in the T-Head TH1520 [1]. Yangtao Li originally submitted this series in May 2023 [2]. Jisheng made additional improvements and then passed on the work in progress to me. Link: https://openbeagle.org/beaglev-ahead/beaglev-ahead/-/blob/main/docs/TH1520%20System%20User%20Manual.pdf [1] Link: https://lore.kernel.org/all/20230515054402.27633-1-frank.li@vivo.com/ [2] Changes in v3: - dt-binding patch has been applied to clk-next by Stephen but I'm keeping it in the series for completeness. - move dt-bindings include after linux includes in driver - change rate to u64 in th1520_pll_vco_recalc_rate() - replace do_div() with normal division operation in both th1520_pll_vco_recalc_rate() and th1520_pll_postdiv_recalc_rate() - add static to ccu_mux structs: c910_i0_clk, c910_clk, uart_sclk Changes in v2: - Add clock property to the gpio nodes after Conor asked why they were missing. These clock gates correspond to enable bits in PERI_CLK_CFG. - Drop 2 cell address and size properties from the binding example per Conor and add Reviewed-by from from Conor. - Link: https://lore.kernel.org/linux-riscv/20240623-th1520-clk-v2-0-ad8d6432d9fb@tenstorrent.com/ Changes in v1: - Split th1520_clks into groups for gate, mux, div, pll - Convert gate clocks to devm_clk_hw_register_gate_parent_data() - Convert mux clocks to devm_clk_hw_register_mux_parent_data_table() - Split the PLL recalculation into th1520_pll_vco_recalc_rate() and th1520_pll_postdiv_recalc_rate(). Based on Emil's comments in v1, add logic to handle the fractional portion of feedback divide value when the delta-sigma modulator (DSM) is active. - Drop clock-names from the binding per Stephan to avoid relying on anything other than the cell index when describing clk_parent_data (note: I dropped Rob's Rb because I changed the binding patch) - Rename reg/reg2 to cfg0/cfg1 to match the SoC documentation - Rename struct for pll clocks from ccu_mdiv to ccu_pll - Rebase on v6.10-rc3, remove the dts node reordering patch from v3 now that it is in mainline - Link: https://lore.kernel.org/linux-riscv/20240615-th1520-clk-v1-0-3ba4978c4d6b@tenstorrent.com/ Changes in RFC v3: - Drop redundant new line and unused clk label from the dts example in the DT binding which I failed to fix in v2. - Add patch [4] from Thomas Bonnefille that fixes dts node ordering in th1520.dtsi. Conor has already merged it into riscv-dt-for-next so the dts patches in this series are based on top of that. - Remove fixed uart clock and converted uart DT nodes to use clocks from the clock controller. - Remove fixed apb clock and converted the dma controller and timer DT nodes to use a clock from the clock controller. - Made ccu_disable_helper() and ccu_enable_helper() to static functions - Follow the advice from Stephen Boyd in Yangtao's original series to not use strings for clk tree topology. Created clk_parent_data arrays to be used with CLK_HW_INIT_PARENTS_DATA instead of parent strings. - Rebase on top of v6.9-rc7 - Link: https://lore.kernel.org/all/20240506-th1520-clk-v3-0-085a18a23a7f@tenstorrent.com/ Changes in RFC v2: - squash the header file patch into the DT schema patch - describe the changes I made to original series in the cover letter instead of the individual patches - fix my typo in my email address - Link: https://lore.kernel.org/all/20240426-th1520-clk-v2-v2-0-96b829e6fcee@tenstorrent.com/ Changes in RFC v1 compared to the original series: - corrected the npu_clk enable bit - deduplicated CLK_NPU and CLK_NPU_AXI number in header - fixed c910_i0_clk reg typo - fixed checkpatch and dt_binding_check warnings - rebased on v6.9-rc5 - revised commit descriptions - Link: https://lore.kernel.org/all/20240110-clk-th1520-v1-0-8b0682567984@tenstorrent.com/ Thank you, Drew --- Drew Fustini (7): dt-bindings: clock: Document T-Head TH1520 AP_SUBSYS controller clk: thead: Add support for T-Head TH1520 AP_SUBSYS clocks riscv: dts: thead: Add TH1520 AP_SUBSYS clock controller riscv: dts: thead: change TH1520 uart nodes to use clock controller riscv: dts: thead: change TH1520 mmc nodes to use clock controller riscv: dts: thead: update TH1520 dma and timer nodes to use clock controller riscv: dts: thead: add clock to TH1520 gpio nodes .../bindings/clock/thead,th1520-clk-ap.yaml | 53 + MAINTAINERS | 3 + arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts | 12 - .../boot/dts/thead/th1520-lichee-module-4a.dtsi | 12 - arch/riscv/boot/dts/thead/th1520.dtsi | 73 +- drivers/clk/Kconfig | 1 + drivers/clk/Makefile | 1 + drivers/clk/thead/Kconfig | 12 + drivers/clk/thead/Makefile | 2 + drivers/clk/thead/clk-th1520-ap.c | 1089 ++++++++++++++++++++ include/dt-bindings/clock/thead,th1520-clk-ap.h | 96 ++ 11 files changed, 1293 insertions(+), 61 deletions(-) --- base-commit: 256abd8e550ce977b728be79a74e1729438b4948 change-id: 20240710-th1520-clk-0ad976e2a42e Best regards,