| Message ID | 20240712083850.4242-3-yongxuan.wang@sifive.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Svade and Svadu Extensions Support | expand |
On Fri, Jul 12, 2024 at 04:38:46PM +0800, Yong-Xuan Wang wrote: > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions > property. > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> Acked-by: Conor Dooley <conor.dooley@microchip.com>
On 12/07/2024 10:38, Yong-Xuan Wang wrote: > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions > property. > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > --- > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 468c646247aa..e91a6f4ede38 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -153,6 +153,34 @@ properties: > ratified at commit 3f9ed34 ("Add ability to manually trigger > workflow. (#2)") of riscv-time-compare. > > + - const: svade > + description: | > + The standard Svade supervisor-level extension for SW-managed PTE A/D > + bit updates as ratified in the 20240213 version of the privileged > + ISA specification. > + > + Both Svade and Svadu extensions control the hardware behavior when > + the PTE A/D bits need to be set. The default behavior for the four > + possible combinations of these extensions in the device tree are: > + 1) Neither Svade nor Svadu present in DT => It is technically > + unknown whether the platform uses Svade or Svadu. Supervisor > + software should be prepared to handle either hardware updating > + of the PTE A/D bits or page faults when they need updated. > + 2) Only Svade present in DT => Supervisor must assume Svade to be > + always enabled. > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be > + always enabled. > + 4) Both Svade and Svadu present in DT => Supervisor must assume > + Svadu turned-off at boot time. To use Svadu, supervisor must > + explicitly enable it using the SBI FWFT extension. > + > + - const: svadu > + description: | > + The standard Svadu supervisor-level extension for hardware updating > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade > + dt-binding description for more details. > + > - const: svinval > description: > The standard Svinval supervisor-level extension for fine-grained Reviewed-by: Alexandre Ghiti <alexghiti@rivosinc.com> Thanks, Alex
On 2024-07-12 3:38 AM, Yong-Xuan Wang wrote: > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions > property. > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > --- > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ > 1 file changed, 28 insertions(+) > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > index 468c646247aa..e91a6f4ede38 100644 > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > @@ -153,6 +153,34 @@ properties: > ratified at commit 3f9ed34 ("Add ability to manually trigger > workflow. (#2)") of riscv-time-compare. > > + - const: svade > + description: | > + The standard Svade supervisor-level extension for SW-managed PTE A/D > + bit updates as ratified in the 20240213 version of the privileged > + ISA specification. > + > + Both Svade and Svadu extensions control the hardware behavior when > + the PTE A/D bits need to be set. The default behavior for the four > + possible combinations of these extensions in the device tree are: > + 1) Neither Svade nor Svadu present in DT => It is technically > + unknown whether the platform uses Svade or Svadu. Supervisor > + software should be prepared to handle either hardware updating > + of the PTE A/D bits or page faults when they need updated. > + 2) Only Svade present in DT => Supervisor must assume Svade to be > + always enabled. > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be > + always enabled. > + 4) Both Svade and Svadu present in DT => Supervisor must assume > + Svadu turned-off at boot time. To use Svadu, supervisor must > + explicitly enable it using the SBI FWFT extension. > + > + - const: svadu > + description: | > + The standard Svadu supervisor-level extension for hardware updating > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade Should we be referencing the archived riscv-svadu repository now that Svadu has been merged to the main privileged ISA manual? Either way: Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > + dt-binding description for more details. > + > - const: svinval > description: > The standard Svinval supervisor-level extension for fine-grained
Hi Samuel, On Fri, Jul 19, 2024 at 7:38 AM Samuel Holland <samuel.holland@sifive.com> wrote: > > On 2024-07-12 3:38 AM, Yong-Xuan Wang wrote: > > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions > > property. > > > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > > --- > > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ > > 1 file changed, 28 insertions(+) > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > > index 468c646247aa..e91a6f4ede38 100644 > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > @@ -153,6 +153,34 @@ properties: > > ratified at commit 3f9ed34 ("Add ability to manually trigger > > workflow. (#2)") of riscv-time-compare. > > > > + - const: svade > > + description: | > > + The standard Svade supervisor-level extension for SW-managed PTE A/D > > + bit updates as ratified in the 20240213 version of the privileged > > + ISA specification. > > + > > + Both Svade and Svadu extensions control the hardware behavior when > > + the PTE A/D bits need to be set. The default behavior for the four > > + possible combinations of these extensions in the device tree are: > > + 1) Neither Svade nor Svadu present in DT => It is technically > > + unknown whether the platform uses Svade or Svadu. Supervisor > > + software should be prepared to handle either hardware updating > > + of the PTE A/D bits or page faults when they need updated. > > + 2) Only Svade present in DT => Supervisor must assume Svade to be > > + always enabled. > > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be > > + always enabled. > > + 4) Both Svade and Svadu present in DT => Supervisor must assume > > + Svadu turned-off at boot time. To use Svadu, supervisor must > > + explicitly enable it using the SBI FWFT extension. > > + > > + - const: svadu > > + description: | > > + The standard Svadu supervisor-level extension for hardware updating > > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request > > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade > > Should we be referencing the archived riscv-svadu repository now that Svadu has > been merged to the main privileged ISA manual? Either way: > > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > Yes, this commit is from the archived riscv-svadu repo. Or should I update it to "commit c1abccf ("Merge pull request #25 from ved-rivos/ratified") of riscvarchive/riscv-svadu."? Regards, Yong-Xuan > > + dt-binding description for more details. > > + > > - const: svinval > > description: > > The standard Svinval supervisor-level extension for fine-grained >
On Fri, Jul 19, 2024 at 02:58:59PM +0800, Yong-Xuan Wang wrote: > Hi Samuel, > > On Fri, Jul 19, 2024 at 7:38 AM Samuel Holland > <samuel.holland@sifive.com> wrote: > > > > On 2024-07-12 3:38 AM, Yong-Xuan Wang wrote: > > > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions > > > property. > > > > > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > > > --- > > > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ > > > 1 file changed, 28 insertions(+) > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > > > index 468c646247aa..e91a6f4ede38 100644 > > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > > @@ -153,6 +153,34 @@ properties: > > > ratified at commit 3f9ed34 ("Add ability to manually trigger > > > workflow. (#2)") of riscv-time-compare. > > > > > > + - const: svade > > > + description: | > > > + The standard Svade supervisor-level extension for SW-managed PTE A/D > > > + bit updates as ratified in the 20240213 version of the privileged > > > + ISA specification. > > > + > > > + Both Svade and Svadu extensions control the hardware behavior when > > > + the PTE A/D bits need to be set. The default behavior for the four > > > + possible combinations of these extensions in the device tree are: > > > + 1) Neither Svade nor Svadu present in DT => It is technically > > > + unknown whether the platform uses Svade or Svadu. Supervisor > > > + software should be prepared to handle either hardware updating > > > + of the PTE A/D bits or page faults when they need updated. > > > + 2) Only Svade present in DT => Supervisor must assume Svade to be > > > + always enabled. > > > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be > > > + always enabled. > > > + 4) Both Svade and Svadu present in DT => Supervisor must assume > > > + Svadu turned-off at boot time. To use Svadu, supervisor must > > > + explicitly enable it using the SBI FWFT extension. > > > + > > > + - const: svadu > > > + description: | > > > + The standard Svadu supervisor-level extension for hardware updating > > > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request > > > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade > > > > Should we be referencing the archived riscv-svadu repository now that Svadu has > > been merged to the main privileged ISA manual? Either way: > > > > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > > > > Yes, this commit is from the archived riscv-svadu repo. Or should I update it to > "commit c1abccf ("Merge pull request #25 from ved-rivos/ratified") of > riscvarchive/riscv-svadu."? I think Samuel was saying that we should use the commit where it was merged into riscv-isa-manual instead.
Hi Conor, On Fri, Jul 19, 2024 at 9:17 PM Conor Dooley <conor@kernel.org> wrote: > > On Fri, Jul 19, 2024 at 02:58:59PM +0800, Yong-Xuan Wang wrote: > > Hi Samuel, > > > > On Fri, Jul 19, 2024 at 7:38 AM Samuel Holland > > <samuel.holland@sifive.com> wrote: > > > > > > On 2024-07-12 3:38 AM, Yong-Xuan Wang wrote: > > > > Add entries for the Svade and Svadu extensions to the riscv,isa-extensions > > > > property. > > > > > > > > Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> > > > > --- > > > > .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ > > > > 1 file changed, 28 insertions(+) > > > > > > > > diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml > > > > index 468c646247aa..e91a6f4ede38 100644 > > > > --- a/Documentation/devicetree/bindings/riscv/extensions.yaml > > > > +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml > > > > @@ -153,6 +153,34 @@ properties: > > > > ratified at commit 3f9ed34 ("Add ability to manually trigger > > > > workflow. (#2)") of riscv-time-compare. > > > > > > > > + - const: svade > > > > + description: | > > > > + The standard Svade supervisor-level extension for SW-managed PTE A/D > > > > + bit updates as ratified in the 20240213 version of the privileged > > > > + ISA specification. > > > > + > > > > + Both Svade and Svadu extensions control the hardware behavior when > > > > + the PTE A/D bits need to be set. The default behavior for the four > > > > + possible combinations of these extensions in the device tree are: > > > > + 1) Neither Svade nor Svadu present in DT => It is technically > > > > + unknown whether the platform uses Svade or Svadu. Supervisor > > > > + software should be prepared to handle either hardware updating > > > > + of the PTE A/D bits or page faults when they need updated. > > > > + 2) Only Svade present in DT => Supervisor must assume Svade to be > > > > + always enabled. > > > > + 3) Only Svadu present in DT => Supervisor must assume Svadu to be > > > > + always enabled. > > > > + 4) Both Svade and Svadu present in DT => Supervisor must assume > > > > + Svadu turned-off at boot time. To use Svadu, supervisor must > > > > + explicitly enable it using the SBI FWFT extension. > > > > + > > > > + - const: svadu > > > > + description: | > > > > + The standard Svadu supervisor-level extension for hardware updating > > > > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request > > > > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade > > > > > > Should we be referencing the archived riscv-svadu repository now that Svadu has > > > been merged to the main privileged ISA manual? Either way: > > > > > > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > > > > > > > Yes, this commit is from the archived riscv-svadu repo. Or should I update it to > > "commit c1abccf ("Merge pull request #25 from ved-rivos/ratified") of > > riscvarchive/riscv-svadu."? > > I think Samuel was saying that we should use the commit where it was > merged into riscv-isa-manual instead. Got it. I will update the description in the next version. Thank you!
On Mon, Jul 22, 2024 at 10:14:11AM +0800, Yong-Xuan Wang wrote: > > > > > + - const: svadu > > > > > + description: | > > > > > + The standard Svadu supervisor-level extension for hardware updating > > > > > + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request > > > > > + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade > > > > > > > > Should we be referencing the archived riscv-svadu repository now that Svadu has > > > > been merged to the main privileged ISA manual? Either way: > > > > > > > > Reviewed-by: Samuel Holland <samuel.holland@sifive.com> > > > > > > > > > > Yes, this commit is from the archived riscv-svadu repo. Or should I update it to > > > "commit c1abccf ("Merge pull request #25 from ved-rivos/ratified") of > > > riscvarchive/riscv-svadu."? > > > > I think Samuel was saying that we should use the commit where it was > > merged into riscv-isa-manual instead. > > Got it. I will update the description in the next version. Thank you! There's no need (IMO) to send a new version for this alone - but if you have to send another version for some other reason then do it. Cheers, Conor.
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml index 468c646247aa..e91a6f4ede38 100644 --- a/Documentation/devicetree/bindings/riscv/extensions.yaml +++ b/Documentation/devicetree/bindings/riscv/extensions.yaml @@ -153,6 +153,34 @@ properties: ratified at commit 3f9ed34 ("Add ability to manually trigger workflow. (#2)") of riscv-time-compare. + - const: svade + description: | + The standard Svade supervisor-level extension for SW-managed PTE A/D + bit updates as ratified in the 20240213 version of the privileged + ISA specification. + + Both Svade and Svadu extensions control the hardware behavior when + the PTE A/D bits need to be set. The default behavior for the four + possible combinations of these extensions in the device tree are: + 1) Neither Svade nor Svadu present in DT => It is technically + unknown whether the platform uses Svade or Svadu. Supervisor + software should be prepared to handle either hardware updating + of the PTE A/D bits or page faults when they need updated. + 2) Only Svade present in DT => Supervisor must assume Svade to be + always enabled. + 3) Only Svadu present in DT => Supervisor must assume Svadu to be + always enabled. + 4) Both Svade and Svadu present in DT => Supervisor must assume + Svadu turned-off at boot time. To use Svadu, supervisor must + explicitly enable it using the SBI FWFT extension. + + - const: svadu + description: | + The standard Svadu supervisor-level extension for hardware updating + of PTE A/D bits as ratified at commit c1abccf ("Merge pull request + #25 from ved-rivos/ratified") of riscv-svadu. Please refer to Svade + dt-binding description for more details. + - const: svinval description: The standard Svinval supervisor-level extension for fine-grained
Add entries for the Svade and Svadu extensions to the riscv,isa-extensions property. Signed-off-by: Yong-Xuan Wang <yongxuan.wang@sifive.com> --- .../devicetree/bindings/riscv/extensions.yaml | 28 +++++++++++++++++++ 1 file changed, 28 insertions(+)