| Message ID | 20240709135152.185042-7-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Add support for RZ/G2UL Display Unit | expand |
Hi Biju, Thank you for the patch. On Tue, Jul 09, 2024 at 02:51:44PM +0100, Biju Das wrote: > Add vspd node to RZ/G2UL SoC DTSI. > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > v1->v2: > * No change. > --- > arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 13 +++++++++++++ > 1 file changed, 13 insertions(+) > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > index 18ef297db933..15e84a5428ef 100644 > --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > @@ -129,6 +129,19 @@ csi2cru: endpoint@0 { > }; > }; > > + vspd: vsp@10870000 { > + compatible = "renesas,r9a07g043u-vsp2", "renesas,r9a07g044-vsp2"; > + reg = <0 0x10870000 0 0x10000>; > + interrupts = <SOC_PERIPHERAL_IRQ(149) IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, > + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, > + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; > + clock-names = "aclk", "pclk", "vclk"; > + power-domains = <&cpg>; > + resets = <&cpg R9A07G043_LCDC_RESET_N>; > + renesas,fcp = <&fcpvd>; This patch looks fine, but I would move it after 7/9, as here you reference a node that doesn't exist yet. Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > + }; > + > irqc: interrupt-controller@110a0000 { > compatible = "renesas,r9a07g043u-irqc", > "renesas,rzg2l-irqc";
Hi Laurent, Thanks for the feedback. > -----Original Message----- > From: Laurent Pinchart <laurent.pinchart@ideasonboard.com> > Sent: Saturday, July 27, 2024 2:08 AM > Subject: Re: [PATCH v2 6/9] arm64: dts: renesas: r9a07g043u: Add vspd node > > Hi Biju, > > Thank you for the patch. > > On Tue, Jul 09, 2024 at 02:51:44PM +0100, Biju Das wrote: > > Add vspd node to RZ/G2UL SoC DTSI. > > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > > --- > > v1->v2: > > * No change. > > --- > > arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 13 +++++++++++++ > > 1 file changed, 13 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > > b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > > index 18ef297db933..15e84a5428ef 100644 > > --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > > +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi > > @@ -129,6 +129,19 @@ csi2cru: endpoint@0 { > > }; > > }; > > > > + vspd: vsp@10870000 { > > + compatible = "renesas,r9a07g043u-vsp2", "renesas,r9a07g044-vsp2"; > > + reg = <0 0x10870000 0 0x10000>; > > + interrupts = <SOC_PERIPHERAL_IRQ(149) IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, > > + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, > > + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; > > + clock-names = "aclk", "pclk", "vclk"; > > + power-domains = <&cpg>; > > + resets = <&cpg R9A07G043_LCDC_RESET_N>; > > + renesas,fcp = <&fcpvd>; > > This patch looks fine, but I would move it after 7/9, as here you reference a node that doesn't exist > yet. Good catch. Will fix this in next version. Cheers, Biju > > Reviewed-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com> > > > + }; > > + > > irqc: interrupt-controller@110a0000 { > > compatible = "renesas,r9a07g043u-irqc", > > "renesas,rzg2l-irqc"; > > -- > Regards, > > Laurent Pinchart
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi index 18ef297db933..15e84a5428ef 100644 --- a/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a07g043u.dtsi @@ -129,6 +129,19 @@ csi2cru: endpoint@0 { }; }; + vspd: vsp@10870000 { + compatible = "renesas,r9a07g043u-vsp2", "renesas,r9a07g044-vsp2"; + reg = <0 0x10870000 0 0x10000>; + interrupts = <SOC_PERIPHERAL_IRQ(149) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&cpg CPG_MOD R9A07G043_LCDC_CLK_A>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_P>, + <&cpg CPG_MOD R9A07G043_LCDC_CLK_D>; + clock-names = "aclk", "pclk", "vclk"; + power-domains = <&cpg>; + resets = <&cpg R9A07G043_LCDC_RESET_N>; + renesas,fcp = <&fcpvd>; + }; + irqc: interrupt-controller@110a0000 { compatible = "renesas,r9a07g043u-irqc", "renesas,rzg2l-irqc";
Add vspd node to RZ/G2UL SoC DTSI. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- v1->v2: * No change. --- arch/arm64/boot/dts/renesas/r9a07g043u.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+)