| Message ID | 20240731062916.2680823-3-quic_skakitap@quicinc.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 4ad1ed6ef27cab94888bb3c740c14042d5c0dff2 |
| Headers | show |
| Series | Add camera clock controller support for SM8150 | expand |
On Wed, Jul 31, 2024 at 11:59:10AM GMT, Satya Priya Kakitapalli wrote: > Correct the pll postdiv shift used in clk_trion_pll_postdiv_set_rate > API. The shift value is not same for different types of plls and > should be taken from the pll's .post_div_shift member. > > Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs") > Cc: stable@vger.kernel.org > Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> > --- > drivers/clk/qcom/clk-alpha-pll.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
diff --git a/drivers/clk/qcom/clk-alpha-pll.c b/drivers/clk/qcom/clk-alpha-pll.c index 9ce45cd6e09f..eb5626095916 100644 --- a/drivers/clk/qcom/clk-alpha-pll.c +++ b/drivers/clk/qcom/clk-alpha-pll.c @@ -1552,8 +1552,8 @@ clk_trion_pll_postdiv_set_rate(struct clk_hw *hw, unsigned long rate, } return regmap_update_bits(regmap, PLL_USER_CTL(pll), - PLL_POST_DIV_MASK(pll) << PLL_POST_DIV_SHIFT, - val << PLL_POST_DIV_SHIFT); + PLL_POST_DIV_MASK(pll) << pll->post_div_shift, + val << pll->post_div_shift); } const struct clk_ops clk_alpha_pll_postdiv_trion_ops = {
Correct the pll postdiv shift used in clk_trion_pll_postdiv_set_rate API. The shift value is not same for different types of plls and should be taken from the pll's .post_div_shift member. Fixes: 548a909597d5 ("clk: qcom: clk-alpha-pll: Add support for Trion PLLs") Cc: stable@vger.kernel.org Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> --- drivers/clk/qcom/clk-alpha-pll.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)