| Message ID | 20240731222831.14895-6-james.quinlan@broadcom.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | PCI: brcnstb: Enable STB 7712 SOC | expand |
On 7/31/24 15:28, Jim Quinlan wrote: > The 7712 SOC adds a software init reset device for the PCIe HW. > If found in the DT node, use it. > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
On Wed, Jul 31, 2024 at 06:28:19PM -0400, Jim Quinlan wrote: > The 7712 SOC adds a software init reset device for the PCIe HW. > If found in the DT node, use it. > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > --- > drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index 4d68fe318178..948fd4d176bc 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -266,6 +266,7 @@ struct brcm_pcie { > struct reset_control *rescal; > struct reset_control *perst_reset; > struct reset_control *bridge_reset; > + struct reset_control *swinit_reset; > int num_memc; > u64 memc_size[PCIE_BRCM_MAX_MEMC]; > u32 hw_rev; > @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev) > if (IS_ERR(pcie->bridge_reset)) > return PTR_ERR(pcie->bridge_reset); > > + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); > + if (IS_ERR(pcie->swinit_reset)) > + return PTR_ERR(pcie->swinit_reset); > + > ret = clk_prepare_enable(pcie->clk); > if (ret) > return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); > > pcie->bridge_sw_init_set(pcie, 0); > > + if (pcie->swinit_reset) { You already have a callback called 'bridge_sw_init_set', so this 'swinit_reset' is different from 'bridge_sw_init'? If so, does it make sense to move this into the callback itself to have all reset sequence in one place? - Mani > + ret = reset_control_assert(pcie->swinit_reset); > + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n")) > + goto clk_disable_unprepare; > + > + /* HW team recommends 1us for proper sync and propagation of reset */ > + udelay(1); > + > + ret = reset_control_deassert(pcie->swinit_reset); > + if (dev_err_probe(&pdev->dev, ret, > + "could not de-assert reset 'swinit' after asserting\n")) > + goto clk_disable_unprepare; > + } > + > ret = reset_control_reset(pcie->rescal); > if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) > goto clk_disable_unprepare; > -- > 2.17.1 >
Hi Jim, On 8/1/24 01:28, Jim Quinlan wrote: > The 7712 SOC adds a software init reset device for the PCIe HW. > If found in the DT node, use it. > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > --- > drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > index 4d68fe318178..948fd4d176bc 100644 > --- a/drivers/pci/controller/pcie-brcmstb.c > +++ b/drivers/pci/controller/pcie-brcmstb.c > @@ -266,6 +266,7 @@ struct brcm_pcie { > struct reset_control *rescal; > struct reset_control *perst_reset; > struct reset_control *bridge_reset; > + struct reset_control *swinit_reset; > int num_memc; > u64 memc_size[PCIE_BRCM_MAX_MEMC]; > u32 hw_rev; > @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev) > if (IS_ERR(pcie->bridge_reset)) > return PTR_ERR(pcie->bridge_reset); > > + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); > + if (IS_ERR(pcie->swinit_reset)) > + return PTR_ERR(pcie->swinit_reset); > + > ret = clk_prepare_enable(pcie->clk); > if (ret) > return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); > > pcie->bridge_sw_init_set(pcie, 0); > > + if (pcie->swinit_reset) { > + ret = reset_control_assert(pcie->swinit_reset); > + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n")) > + goto clk_disable_unprepare; > + > + /* HW team recommends 1us for proper sync and propagation of reset */ > + udelay(1); Hmm, shouldn't this delay be part of .assert/.deassert reset_control driver? I think this detail is reset-control hw specific and the consumers does not need to know it. > + > + ret = reset_control_deassert(pcie->swinit_reset); > + if (dev_err_probe(&pdev->dev, ret, > + "could not de-assert reset 'swinit' after asserting\n")) > + goto clk_disable_unprepare; > + } > + > ret = reset_control_reset(pcie->rescal); > if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) > goto clk_disable_unprepare; ~Stan
On Fri, Aug 9, 2024 at 5:53 AM Stanimir Varbanov <svarbanov@suse.de> wrote: > > Hi Jim, > > On 8/1/24 01:28, Jim Quinlan wrote: > > The 7712 SOC adds a software init reset device for the PCIe HW. > > If found in the DT node, use it. > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > > --- > > drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++ > > 1 file changed, 19 insertions(+) > > > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > > index 4d68fe318178..948fd4d176bc 100644 > > --- a/drivers/pci/controller/pcie-brcmstb.c > > +++ b/drivers/pci/controller/pcie-brcmstb.c > > @@ -266,6 +266,7 @@ struct brcm_pcie { > > struct reset_control *rescal; > > struct reset_control *perst_reset; > > struct reset_control *bridge_reset; > > + struct reset_control *swinit_reset; > > int num_memc; > > u64 memc_size[PCIE_BRCM_MAX_MEMC]; > > u32 hw_rev; > > @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev) > > if (IS_ERR(pcie->bridge_reset)) > > return PTR_ERR(pcie->bridge_reset); > > > > + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); > > + if (IS_ERR(pcie->swinit_reset)) > > + return PTR_ERR(pcie->swinit_reset); > > + > > ret = clk_prepare_enable(pcie->clk); > > if (ret) > > return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); > > > > pcie->bridge_sw_init_set(pcie, 0); > > > > + if (pcie->swinit_reset) { > > + ret = reset_control_assert(pcie->swinit_reset); > > + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n")) > > + goto clk_disable_unprepare; > > + > > + /* HW team recommends 1us for proper sync and propagation of reset */ > > + udelay(1); > > Hmm, shouldn't this delay be part of .assert/.deassert reset_control > driver? I think this detail is reset-control hw specific and the > consumers does not need to know it. This was discussed previously. I pointed out that we use a reset provider that governs dozens of devices. The only thing that the provider could do is to employ a worst case delay used for all resets. This is unacceptable; we have certain devices that may have to invoke reset often and require timely action, and we do not want them having to wait the same amount of worst case delay as for example, a UART device reset. Further, if I do a "grep reset_control_assert -A 10 drivers" I see plenty of existing drivers that use usleep/msleep/udelay after the call to reset_control_assert, just as I am doing now. As far as my opinion goes (FWIW) I think the delay is more apt to be present in the consumer driver and not the provider driver. To ascertain this specific delay I had to consult with the PCIe HW team, not the HW team that implemented the reset controller. Regards, Jim Quinlan Broadcom > > > + > > + ret = reset_control_deassert(pcie->swinit_reset); > > + if (dev_err_probe(&pdev->dev, ret, > > + "could not de-assert reset 'swinit' after asserting\n")) > > + goto clk_disable_unprepare; > > + } > > + > > ret = reset_control_reset(pcie->rescal); > > if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) > > goto clk_disable_unprepare; > > ~Stan
On Mon, Aug 12, 2024 at 09:43:46AM -0400, Jim Quinlan wrote: > On Fri, Aug 9, 2024 at 5:53 AM Stanimir Varbanov <svarbanov@suse.de> wrote: > > > > Hi Jim, > > > > On 8/1/24 01:28, Jim Quinlan wrote: > > > The 7712 SOC adds a software init reset device for the PCIe HW. > > > If found in the DT node, use it. > > > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > > > --- > > > drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++ > > > 1 file changed, 19 insertions(+) > > > > > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > > > index 4d68fe318178..948fd4d176bc 100644 > > > --- a/drivers/pci/controller/pcie-brcmstb.c > > > +++ b/drivers/pci/controller/pcie-brcmstb.c > > > @@ -266,6 +266,7 @@ struct brcm_pcie { > > > struct reset_control *rescal; > > > struct reset_control *perst_reset; > > > struct reset_control *bridge_reset; > > > + struct reset_control *swinit_reset; > > > int num_memc; > > > u64 memc_size[PCIE_BRCM_MAX_MEMC]; > > > u32 hw_rev; > > > @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev) > > > if (IS_ERR(pcie->bridge_reset)) > > > return PTR_ERR(pcie->bridge_reset); > > > > > > + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); > > > + if (IS_ERR(pcie->swinit_reset)) > > > + return PTR_ERR(pcie->swinit_reset); > > > + > > > ret = clk_prepare_enable(pcie->clk); > > > if (ret) > > > return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); > > > > > > pcie->bridge_sw_init_set(pcie, 0); > > > > > > + if (pcie->swinit_reset) { > > > + ret = reset_control_assert(pcie->swinit_reset); > > > + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n")) > > > + goto clk_disable_unprepare; > > > + > > > + /* HW team recommends 1us for proper sync and propagation of reset */ > > > + udelay(1); > > > > Hmm, shouldn't this delay be part of .assert/.deassert reset_control > > driver? I think this detail is reset-control hw specific and the > > consumers does not need to know it. > > This was discussed previously. I pointed out that we use a reset > provider that governs dozens of devices. The only thing that the > provider could do is to employ a worst case delay used for all > resets. This is unacceptable; we have certain devices that may have > to invoke > reset often and require timely action, and we do not want them having > to wait the same amount of worst case delay as for example, a UART device reset. > > Further, if I do a "grep reset_control_assert -A 10 drivers" I see > plenty of existing drivers that use usleep/msleep/udelay after the call to > reset_control_assert, just as I am doing now. > > As far as my opinion goes (FWIW) I think the delay is more apt to > be present in the consumer driver and not the provider driver. To > ascertain this specific delay I had to consult with the PCIe HW team, > not the HW team that implemented the reset controller. > Yeah. Often the reset controller won't have any idea about the delay required between assert + deassert, unless the reset controller is closely tied to the peripheral. So keeping the delay in consumer drivers is the right thing to do. - Mani
On Tue, Aug 6, 2024 at 11:03 PM Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> wrote: > > On Wed, Jul 31, 2024 at 06:28:19PM -0400, Jim Quinlan wrote: > > The 7712 SOC adds a software init reset device for the PCIe HW. > > If found in the DT node, use it. > > > > Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> > > --- > > drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++ > > 1 file changed, 19 insertions(+) > > > > diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c > > index 4d68fe318178..948fd4d176bc 100644 > > --- a/drivers/pci/controller/pcie-brcmstb.c > > +++ b/drivers/pci/controller/pcie-brcmstb.c > > @@ -266,6 +266,7 @@ struct brcm_pcie { > > struct reset_control *rescal; > > struct reset_control *perst_reset; > > struct reset_control *bridge_reset; > > + struct reset_control *swinit_reset; > > int num_memc; > > u64 memc_size[PCIE_BRCM_MAX_MEMC]; > > u32 hw_rev; > > @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev) > > if (IS_ERR(pcie->bridge_reset)) > > return PTR_ERR(pcie->bridge_reset); > > > > + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); > > + if (IS_ERR(pcie->swinit_reset)) > > + return PTR_ERR(pcie->swinit_reset); > > + > > ret = clk_prepare_enable(pcie->clk); > > if (ret) > > return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); > > > > pcie->bridge_sw_init_set(pcie, 0); > > > > + if (pcie->swinit_reset) { > > You already have a callback called 'bridge_sw_init_set', so this 'swinit_reset' > is different from 'bridge_sw_init'? Yes. The swinit_reset is a soft reset of the entire core while bridge_sw_init reset is only for the bridge to system memory. If so, does it make sense to move this into > the callback itself to have all reset sequence in one place? The order and placement of the resets can sometimes be fragile and I would prefer to leave them where they are. Regards, Jim Quinlan Broadcom STB/CM > > - Mani > > > + ret = reset_control_assert(pcie->swinit_reset); > > + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n")) > > + goto clk_disable_unprepare; > > + > > + /* HW team recommends 1us for proper sync and propagation of reset */ > > + udelay(1); > > + > > + ret = reset_control_deassert(pcie->swinit_reset); > > + if (dev_err_probe(&pdev->dev, ret, > > + "could not de-assert reset 'swinit' after asserting\n")) > > + goto clk_disable_unprepare; > > + } > > + > > ret = reset_control_reset(pcie->rescal); > > if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) > > goto clk_disable_unprepare; > > -- > > 2.17.1 > > > > -- > மணிவண்ணன் சதாசிவம்
Hi, On 8/12/24 16:43, Jim Quinlan wrote: > On Fri, Aug 9, 2024 at 5:53 AM Stanimir Varbanov <svarbanov@suse.de> wrote: >> >> Hi Jim, >> >> On 8/1/24 01:28, Jim Quinlan wrote: >>> The 7712 SOC adds a software init reset device for the PCIe HW. >>> If found in the DT node, use it. >>> >>> Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> >>> --- >>> drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++ >>> 1 file changed, 19 insertions(+) >>> >>> diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c >>> index 4d68fe318178..948fd4d176bc 100644 >>> --- a/drivers/pci/controller/pcie-brcmstb.c >>> +++ b/drivers/pci/controller/pcie-brcmstb.c >>> @@ -266,6 +266,7 @@ struct brcm_pcie { >>> struct reset_control *rescal; >>> struct reset_control *perst_reset; >>> struct reset_control *bridge_reset; >>> + struct reset_control *swinit_reset; >>> int num_memc; >>> u64 memc_size[PCIE_BRCM_MAX_MEMC]; >>> u32 hw_rev; >>> @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev) >>> if (IS_ERR(pcie->bridge_reset)) >>> return PTR_ERR(pcie->bridge_reset); >>> >>> + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); >>> + if (IS_ERR(pcie->swinit_reset)) >>> + return PTR_ERR(pcie->swinit_reset); >>> + >>> ret = clk_prepare_enable(pcie->clk); >>> if (ret) >>> return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); >>> >>> pcie->bridge_sw_init_set(pcie, 0); >>> >>> + if (pcie->swinit_reset) { >>> + ret = reset_control_assert(pcie->swinit_reset); >>> + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n")) >>> + goto clk_disable_unprepare; >>> + >>> + /* HW team recommends 1us for proper sync and propagation of reset */ >>> + udelay(1); >> >> Hmm, shouldn't this delay be part of .assert/.deassert reset_control >> driver? I think this detail is reset-control hw specific and the >> consumers does not need to know it. > > This was discussed previously. I pointed out that we use a reset Sorry, I missed that discussion. > provider that governs dozens of devices. The only thing that the > provider could do is to employ a worst case delay used for all > resets. This is unacceptable; we have certain devices that may have > to invoke > reset often and require timely action, and we do not want them having > to wait the same amount of worst case delay as for example, a UART device reset. > > Further, if I do a "grep reset_control_assert -A 10 drivers" I see > plenty of existing drivers that use usleep/msleep/udelay after the call to > reset_control_assert, just as I am doing now. Yes, I saw them. > > As far as my opinion goes (FWIW) I think the delay is more apt to > be present in the consumer driver and not the provider driver. To > ascertain this specific delay I had to consult with the PCIe HW team, > not the HW team that implemented the reset controller. > Thank you for the explanation! ~Stan
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c index 4d68fe318178..948fd4d176bc 100644 --- a/drivers/pci/controller/pcie-brcmstb.c +++ b/drivers/pci/controller/pcie-brcmstb.c @@ -266,6 +266,7 @@ struct brcm_pcie { struct reset_control *rescal; struct reset_control *perst_reset; struct reset_control *bridge_reset; + struct reset_control *swinit_reset; int num_memc; u64 memc_size[PCIE_BRCM_MAX_MEMC]; u32 hw_rev; @@ -1633,12 +1634,30 @@ static int brcm_pcie_probe(struct platform_device *pdev) if (IS_ERR(pcie->bridge_reset)) return PTR_ERR(pcie->bridge_reset); + pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); + if (IS_ERR(pcie->swinit_reset)) + return PTR_ERR(pcie->swinit_reset); + ret = clk_prepare_enable(pcie->clk); if (ret) return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); pcie->bridge_sw_init_set(pcie, 0); + if (pcie->swinit_reset) { + ret = reset_control_assert(pcie->swinit_reset); + if (dev_err_probe(&pdev->dev, ret, "could not assert reset 'swinit'\n")) + goto clk_disable_unprepare; + + /* HW team recommends 1us for proper sync and propagation of reset */ + udelay(1); + + ret = reset_control_deassert(pcie->swinit_reset); + if (dev_err_probe(&pdev->dev, ret, + "could not de-assert reset 'swinit' after asserting\n")) + goto clk_disable_unprepare; + } + ret = reset_control_reset(pcie->rescal); if (dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n")) goto clk_disable_unprepare;
The 7712 SOC adds a software init reset device for the PCIe HW. If found in the DT node, use it. Signed-off-by: Jim Quinlan <james.quinlan@broadcom.com> --- drivers/pci/controller/pcie-brcmstb.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)