| Message ID | 20240805-imx8mp-tpm-v1-1-1e89f0268999@phytec.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: freescale: imx8mp-phyboard-pollux: Add and enable TPM | expand |
Hi Benjamin, On Mon, Aug 5, 2024 at 10:33 AM Benjamin Hahn <B.Hahn@phytec.de> wrote: > +/* TPM */ > +&ecspi1 { > + #address-cells = <1>; > + #size-cells = <0>; > + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; > + num-cs = <1>; num-cs is not needed. The number of chip selects can be retrieved from cs-gpios. > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; > + status = "okay"; > + > + tpm: tpm_tis@0 { Node names should be generic. Documentation/devicetree/bindings/tpm/tcg,tpm_tis-spi.yaml suggests 'tpm', so: tpm: tmp@0 { > &iomuxc { > + pinctrl_ecspi1: ecspi1grp { > + fsl,pins = < > + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x80 > + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x80 > + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x80 > + >; > + }; > + > + pinctrl_ecspi1_cs: ecspi1csgrp { > + fsl,pins = < > + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x00 Maybe simpler to put MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 as part of pinctrl_ecspi1.
On Mon, 05 Aug 2024 15:33:27 +0200, Benjamin Hahn wrote: > Add support for TPM for phyBOARD Pollux. > > Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de> > --- > .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 32 ++++++++++++++++++++++ > 1 file changed, 32 insertions(+) > My bot found new DTB warnings on the .dts files added or changed in this series. Some warnings may be from an existing SoC .dtsi. Or perhaps the warnings are fixed by another series. Ultimately, it is up to the platform maintainer whether these warnings are acceptable or not. No need to reply unless the platform maintainer has comments. If you already ran DT checks and didn't see these error(s), then make sure dt-schema is up to date: pip3 install dtschema --upgrade New warnings running 'make CHECK_DTBS=y freescale/imx8mp-phyboard-pollux-rdk.dtb' for 20240805-imx8mp-tpm-v1-1-1e89f0268999@phytec.de: arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dtb: tpm_tis@0: $nodename:0: 'tpm_tis@0' does not match '^tpm(@[0-9a-f]+)?$' from schema $id: http://devicetree.org/schemas/tpm/tcg,tpm_tis-spi.yaml#
diff --git a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts index 00a240484c25..b5ee4e265d90 100644 --- a/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts +++ b/arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts @@ -103,6 +103,24 @@ reg_vcc_3v3_sw: regulator-vcc-3v3-sw { }; }; +/* TPM */ +&ecspi1 { + #address-cells = <1>; + #size-cells = <0>; + cs-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; + num-cs = <1>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1 &pinctrl_ecspi1_cs>; + status = "okay"; + + tpm: tpm_tis@0 { + compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; + reg = <0>; + spi-max-frequency = <38000000>; + status = "okay"; + }; +}; + &eqos { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_eqos>; @@ -300,6 +318,20 @@ &gpio4 { }; &iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_MISO__ECSPI1_MISO 0x80 + MX8MP_IOMUXC_ECSPI1_MOSI__ECSPI1_MOSI 0x80 + MX8MP_IOMUXC_ECSPI1_SCLK__ECSPI1_SCLK 0x80 + >; + }; + + pinctrl_ecspi1_cs: ecspi1csgrp { + fsl,pins = < + MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x00 + >; + }; + pinctrl_eqos: eqosgrp { fsl,pins = < MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
Add support for TPM for phyBOARD Pollux. Signed-off-by: Benjamin Hahn <B.Hahn@phytec.de> --- .../dts/freescale/imx8mp-phyboard-pollux-rdk.dts | 32 ++++++++++++++++++++++ 1 file changed, 32 insertions(+) --- base-commit: 17712b7ea0756799635ba159cc773082230ed028 change-id: 20240805-imx8mp-tpm-3df607b1f5f1 Best regards,