Message ID | 1722218205-10683-2-git-send-email-hongxing.zhu@nxp.com (mailing list archive) |
---|---|
State | Superseded |
Headers | show |
Series | Add dbi2 and atu for i.MX8M PCIe EP | expand |
On Mon, 29 Jul 2024 09:56:42 +0800, Richard Zhu wrote: > Add reg-name: "dbi2", "atu" for i.MX8M PCIe Endpoint. > > For i.MX8M PCIe EP, the dbi2 and atu addresses are pre-defined in the > driver. This method is not good. > > In commit b7d67c6130ee ("PCI: imx6: Add iMX95 Endpoint (EP) support"), > Frank suggests to fetch the dbi2 and atu from DT directly. This commit is > preparation to do that for i.MX8M PCIe EP. > > These changes wouldn't break driver function. When "dbi2" and "atu" > properties are present, i.MX PCIe driver would fetch the according base > addresses from DT directly. If only two reg properties are provided, i.MX > PCIe driver would fall back to the old method. > > Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> > Reviewed-by: Frank Li <Frank.Li@nxp.com> > --- > .../devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml | 13 +++++++++---- > 1 file changed, 9 insertions(+), 4 deletions(-) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml index a06f75df8458..84ca12e8b25b 100644 --- a/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml +++ b/Documentation/devicetree/bindings/pci/fsl,imx6q-pcie-ep.yaml @@ -65,12 +65,14 @@ allOf: then: properties: reg: - minItems: 2 - maxItems: 2 + minItems: 4 + maxItems: 4 reg-names: items: - const: dbi - const: addr_space + - const: dbi2 + - const: atu - if: properties: @@ -129,8 +131,11 @@ examples: pcie_ep: pcie-ep@33800000 { compatible = "fsl,imx8mp-pcie-ep"; - reg = <0x33800000 0x000400000>, <0x18000000 0x08000000>; - reg-names = "dbi", "addr_space"; + reg = <0x33800000 0x100000>, + <0x18000000 0x8000000>, + <0x33900000 0x100000>, + <0x33b00000 0x100000>; + reg-names = "dbi", "addr_space", "dbi2", "atu"; clocks = <&clk IMX8MP_CLK_HSIO_ROOT>, <&clk IMX8MP_CLK_HSIO_AXI>, <&clk IMX8MP_CLK_PCIE_ROOT>;