diff mbox series

[v2,6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes

Message ID 20240811204955.270231-7-prabhakar.mahadev-lad.rj@bp.renesas.com (mailing list archive)
State Superseded
Delegated to: Geert Uytterhoeven
Headers show
Series Add support for Renesas RZ/V2H(P) SoC and GP-EVK platform | expand

Commit Message

Lad, Prabhakar Aug. 11, 2024, 8:49 p.m. UTC 
From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>

Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
v1->v2
- New patch
---
 arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
 1 file changed, 44 insertions(+)

Comments

Biju Das Aug. 12, 2024, 12:25 p.m. UTC | #1 
Hi Prabhakar,

> -----Original Message-----
> From: Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Sunday, August 11, 2024 9:50 PM
> Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> 
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> 
> Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> 
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v2
> - New patch
> ---
>  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
>  1 file changed, 44 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> index 435b1f4e7d38..7f4e8ad9b0a5 100644
> --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> @@ -184,6 +184,17 @@ scif: serial@11c01400 {
>  			status = "disabled";
>  		};
> 
> +		wdt0: watchdog@11c00400 {
> +			compatible = "renesas,r9a09g057-wdt";
> +			reg = <0 0x11c00400 0 0x400>;
> +			clocks = <&cpg CPG_MOD 75>,
> +				 <&cpg CPG_MOD 76>;
> +			clock-names = "pclk", "oscclk";
> +			resets = <&cpg 117>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +		};
> +
>  		ostm4: timer@12c00000 {
>  			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
>  			reg = <0x0 0x12c00000 0x0 0x1000>;
> @@ -224,6 +235,28 @@ ostm7: timer@12c03000 {
>  			status = "disabled";
>  		};
> 
> +		wdt2: watchdog@13000000 {
> +			compatible = "renesas,r9a09g057-wdt";
> +			reg = <0 0x13000000 0 0x400>;
> +			clocks = <&cpg CPG_MOD 79>,
> +				 <&cpg CPG_MOD 80>;
> +			clock-names = "pclk", "oscclk";
> +			resets = <&cpg 119>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +		};

I guess same group(all wdt together) arranged together?? Not sure.

Cheers,
Biju

> +
> +		wdt3: watchdog@13000400 {
> +			compatible = "renesas,r9a09g057-wdt";
> +			reg = <0 0x13000400 0 0x400>;
> +			clocks = <&cpg CPG_MOD 81>,
> +				 <&cpg CPG_MOD 82>;
> +			clock-names = "pclk", "oscclk";
> +			resets = <&cpg 120>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +		};
> +
>  		ostm2: timer@14000000 {
>  			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
>  			reg = <0x0 0x14000000 0x0 0x1000>;
> @@ -244,6 +277,17 @@ ostm3: timer@14001000 {
>  			status = "disabled";
>  		};
> 
> +		wdt1: watchdog@14400000 {
> +			compatible = "renesas,r9a09g057-wdt";
> +			reg = <0 0x14400000 0 0x400>;
> +			clocks = <&cpg CPG_MOD 77>,
> +				 <&cpg CPG_MOD 78>;
> +			clock-names = "pclk", "oscclk";
> +			resets = <&cpg 118>;
> +			power-domains = <&cpg>;
> +			status = "disabled";
> +		};
> +
>  		i2c0: i2c@14400400 {
>  			#address-cells = <1>;
>  			#size-cells = <0>;
> --
> 2.34.1
Lad, Prabhakar Aug. 12, 2024, 12:31 p.m. UTC | #2 
Hi Biju,

On Mon, Aug 12, 2024 at 1:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
>
> Hi Prabhakar,
>
> > -----Original Message-----
> > From: Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Sunday, August 11, 2024 9:50 PM
> > Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> >
> > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> >
> > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> >
> > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > v1->v2
> > - New patch
> > ---
> >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
> >  1 file changed, 44 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > index 435b1f4e7d38..7f4e8ad9b0a5 100644
> > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > @@ -184,6 +184,17 @@ scif: serial@11c01400 {
> >                       status = "disabled";
> >               };
> >
> > +             wdt0: watchdog@11c00400 {
> > +                     compatible = "renesas,r9a09g057-wdt";
> > +                     reg = <0 0x11c00400 0 0x400>;
> > +                     clocks = <&cpg CPG_MOD 75>,
> > +                              <&cpg CPG_MOD 76>;
> > +                     clock-names = "pclk", "oscclk";
> > +                     resets = <&cpg 117>;
> > +                     power-domains = <&cpg>;
> > +                     status = "disabled";
> > +             };
> > +
> >               ostm4: timer@12c00000 {
> >                       compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> >                       reg = <0x0 0x12c00000 0x0 0x1000>;
> > @@ -224,6 +235,28 @@ ostm7: timer@12c03000 {
> >                       status = "disabled";
> >               };
> >
> > +             wdt2: watchdog@13000000 {
> > +                     compatible = "renesas,r9a09g057-wdt";
> > +                     reg = <0 0x13000000 0 0x400>;
> > +                     clocks = <&cpg CPG_MOD 79>,
> > +                              <&cpg CPG_MOD 80>;
> > +                     clock-names = "pclk", "oscclk";
> > +                     resets = <&cpg 119>;
> > +                     power-domains = <&cpg>;
> > +                     status = "disabled";
> > +             };
>
> I guess same group(all wdt together) arranged together?? Not sure.
>
I think Geert prefers it to be sorted based on unit address. So I'll
let Geert make a decision on this (and the rest of the similar patches
where nodes are sorted based on unit address and not grouped based on
IP).

Cheers,
Prabhakar
Biju Das Aug. 12, 2024, 12:39 p.m. UTC | #3 
> -----Original Message-----
> From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Sent: Monday, August 12, 2024 1:32 PM
> To: Biju Das <biju.das.jz@bp.renesas.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm <magnus.damm@gmail.com>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Fabrizio
> Castro <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>
> Subject: Re: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> 
> Hi Biju,
> 
> On Mon, Aug 12, 2024 at 1:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> >
> > Hi Prabhakar,
> >
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Sunday, August 11, 2024 9:50 PM
> > > Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add
> > > WDT0-WDT3 nodes
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar
> > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2
> > > - New patch
> > > ---
> > >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44
> > > ++++++++++++++++++++++
> > >  1 file changed, 44 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > index 435b1f4e7d38..7f4e8ad9b0a5 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > @@ -184,6 +184,17 @@ scif: serial@11c01400 {
> > >                       status = "disabled";
> > >               };
> > >
> > > +             wdt0: watchdog@11c00400 {
> > > +                     compatible = "renesas,r9a09g057-wdt";
> > > +                     reg = <0 0x11c00400 0 0x400>;
> > > +                     clocks = <&cpg CPG_MOD 75>,
> > > +                              <&cpg CPG_MOD 76>;
> > > +                     clock-names = "pclk", "oscclk";
> > > +                     resets = <&cpg 117>;
> > > +                     power-domains = <&cpg>;
> > > +                     status = "disabled";
> > > +             };
> > > +
> > >               ostm4: timer@12c00000 {
> > >                       compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> > >                       reg = <0x0 0x12c00000 0x0 0x1000>; @@ -224,6
> > > +235,28 @@ ostm7: timer@12c03000 {
> > >                       status = "disabled";
> > >               };
> > >
> > > +             wdt2: watchdog@13000000 {
> > > +                     compatible = "renesas,r9a09g057-wdt";
> > > +                     reg = <0 0x13000000 0 0x400>;
> > > +                     clocks = <&cpg CPG_MOD 79>,
> > > +                              <&cpg CPG_MOD 80>;
> > > +                     clock-names = "pclk", "oscclk";
> > > +                     resets = <&cpg 119>;
> > > +                     power-domains = <&cpg>;
> > > +                     status = "disabled";
> > > +             };
> >
> > I guess same group(all wdt together) arranged together?? Not sure.
> >
> I think Geert prefers it to be sorted based on unit address. So I'll let Geert make a decision on this
> (and the rest of the similar patches where nodes are sorted based on unit address and not grouped
> based on IP).

I agree. If that is the case we need to fix [1]
[1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r8a774a1.dtsi?h=next-20240812#n584
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r8a77960.dtsi?h=next-20240812#n633

Cheers,
Biju
Biju Das Aug. 12, 2024, 12:42 p.m. UTC | #4 
> -----Original Message-----
> From: Biju Das
> Sent: Monday, August 12, 2024 1:40 PM
> To: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm <magnus.damm@gmail.com>; Rob Herring
> <robh@kernel.org>; Krzysztof Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Fabrizio
> Castro <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad <prabhakar.mahadev-
> lad.rj@bp.renesas.com>
> Subject: RE: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> 
> 
> 
> > -----Original Message-----
> > From: Lad, Prabhakar <prabhakar.csengg@gmail.com>
> > Sent: Monday, August 12, 2024 1:32 PM
> > To: Biju Das <biju.das.jz@bp.renesas.com>
> > Cc: Geert Uytterhoeven <geert+renesas@glider.be>; Magnus Damm
> > <magnus.damm@gmail.com>; Rob Herring <robh@kernel.org>; Krzysztof
> > Kozlowski <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>;
> > linux-renesas-soc@vger.kernel.org; devicetree@vger.kernel.org;
> > linux-kernel@vger.kernel.org; Fabrizio Castro
> > <fabrizio.castro.jz@renesas.com>; Prabhakar Mahadev Lad
> > <prabhakar.mahadev- lad.rj@bp.renesas.com>
> > Subject: Re: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add
> > WDT0-WDT3 nodes
> >
> > Hi Biju,
> >
> > On Mon, Aug 12, 2024 at 1:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > >
> > > Hi Prabhakar,
> > >
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Sunday, August 11, 2024 9:50 PM
> > > > Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add
> > > > WDT0-WDT3 nodes
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> > > >
> > > > Signed-off-by: Lad Prabhakar
> > > > <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v1->v2
> > > > - New patch
> > > > ---
> > > >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44
> > > > ++++++++++++++++++++++
> > > >  1 file changed, 44 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > index 435b1f4e7d38..7f4e8ad9b0a5 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > @@ -184,6 +184,17 @@ scif: serial@11c01400 {
> > > >                       status = "disabled";
> > > >               };
> > > >
> > > > +             wdt0: watchdog@11c00400 {
> > > > +                     compatible = "renesas,r9a09g057-wdt";
> > > > +                     reg = <0 0x11c00400 0 0x400>;
> > > > +                     clocks = <&cpg CPG_MOD 75>,
> > > > +                              <&cpg CPG_MOD 76>;
> > > > +                     clock-names = "pclk", "oscclk";
> > > > +                     resets = <&cpg 117>;
> > > > +                     power-domains = <&cpg>;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +
> > > >               ostm4: timer@12c00000 {
> > > >                       compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> > > >                       reg = <0x0 0x12c00000 0x0 0x1000>; @@ -224,6
> > > > +235,28 @@ ostm7: timer@12c03000 {
> > > >                       status = "disabled";
> > > >               };
> > > >
> > > > +             wdt2: watchdog@13000000 {
> > > > +                     compatible = "renesas,r9a09g057-wdt";
> > > > +                     reg = <0 0x13000000 0 0x400>;
> > > > +                     clocks = <&cpg CPG_MOD 79>,
> > > > +                              <&cpg CPG_MOD 80>;
> > > > +                     clock-names = "pclk", "oscclk";
> > > > +                     resets = <&cpg 119>;
> > > > +                     power-domains = <&cpg>;
> > > > +                     status = "disabled";
> > > > +             };
> > >
> > > I guess same group(all wdt together) arranged together?? Not sure.
> > >
> > I think Geert prefers it to be sorted based on unit address. So I'll
> > let Geert make a decision on this (and the rest of the similar patches
> > where nodes are sorted based on unit address and not grouped based on IP).
> 
> I agree. If that is the case we need to fix [1] [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-
> next.git/tree/arch/arm64/boot/dts/renesas/r8a774a1.dtsi?h=next-20240812#n584
> https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-
> next.git/tree/arch/arm64/boot/dts/renesas/r8a77960.dtsi?h=next-20240812#n633

Similarly 

https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/arch/arm64/boot/dts/renesas/r8a77960.dtsi?h=next-20240812#n762

Cheers,
Biju
Geert Uytterhoeven Aug. 19, 2024, 1:58 p.m. UTC | #5 
Hi Prabhakar,

On Mon, Aug 12, 2024 at 2:32 PM Lad, Prabhakar
<prabhakar.csengg@gmail.com> wrote:
> On Mon, Aug 12, 2024 at 1:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > -----Original Message-----
> > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > Sent: Sunday, August 11, 2024 9:50 PM
> > > Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> > >
> > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > >
> > > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> > >
> > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > ---
> > > v1->v2
> > > - New patch
> > > ---
> > >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
> > >  1 file changed, 44 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > index 435b1f4e7d38..7f4e8ad9b0a5 100644
> > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > @@ -184,6 +184,17 @@ scif: serial@11c01400 {
> > >                       status = "disabled";
> > >               };
> > >
> > > +             wdt0: watchdog@11c00400 {
> > > +                     compatible = "renesas,r9a09g057-wdt";
> > > +                     reg = <0 0x11c00400 0 0x400>;
> > > +                     clocks = <&cpg CPG_MOD 75>,
> > > +                              <&cpg CPG_MOD 76>;
> > > +                     clock-names = "pclk", "oscclk";
> > > +                     resets = <&cpg 117>;
> > > +                     power-domains = <&cpg>;
> > > +                     status = "disabled";
> > > +             };
> > > +
> > >               ostm4: timer@12c00000 {
> > >                       compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> > >                       reg = <0x0 0x12c00000 0x0 0x1000>;
> > > @@ -224,6 +235,28 @@ ostm7: timer@12c03000 {
> > >                       status = "disabled";
> > >               };
> > >
> > > +             wdt2: watchdog@13000000 {
> > > +                     compatible = "renesas,r9a09g057-wdt";
> > > +                     reg = <0 0x13000000 0 0x400>;
> > > +                     clocks = <&cpg CPG_MOD 79>,
> > > +                              <&cpg CPG_MOD 80>;
> > > +                     clock-names = "pclk", "oscclk";
> > > +                     resets = <&cpg 119>;
> > > +                     power-domains = <&cpg>;
> > > +                     status = "disabled";
> > > +             };
> >
> > I guess same group(all wdt together) arranged together?? Not sure.
> >
> I think Geert prefers it to be sorted based on unit address. So I'll
> let Geert make a decision on this (and the rest of the similar patches
> where nodes are sorted based on unit address and not grouped based on
> IP).

Sorted based on unit-address, but keep all nodes of the same type together.
I.e.:
    wdt0: watchdog@11c00400 { ... };
    wdt2: watchdog@13000000 { ... };
    wdt3: watchdog@13000400 { ... };
    wdt1: watchdog@14400000 { ... };

Thanks!

Gr{oetje,eeting}s,

                        Geert
Lad, Prabhakar Aug. 19, 2024, 2:01 p.m. UTC | #6 
Hi Geert,

On Mon, Aug 19, 2024 at 2:58 PM Geert Uytterhoeven <geert@linux-m68k.org> wrote:
>
> Hi Prabhakar,
>
> On Mon, Aug 12, 2024 at 2:32 PM Lad, Prabhakar
> <prabhakar.csengg@gmail.com> wrote:
> > On Mon, Aug 12, 2024 at 1:25 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > > > -----Original Message-----
> > > > From: Prabhakar <prabhakar.csengg@gmail.com>
> > > > Sent: Sunday, August 11, 2024 9:50 PM
> > > > Subject: [PATCH v2 6/8] arm64: dts: renesas: r9a09g057: Add WDT0-WDT3 nodes
> > > >
> > > > From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > >
> > > > Add WDT0-WDT3 nodes to RZ/V2H(P) ("R9A09G057") SoC DTSI.
> > > >
> > > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > > > ---
> > > > v1->v2
> > > > - New patch
> > > > ---
> > > >  arch/arm64/boot/dts/renesas/r9a09g057.dtsi | 44 ++++++++++++++++++++++
> > > >  1 file changed, 44 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > index 435b1f4e7d38..7f4e8ad9b0a5 100644
> > > > --- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > +++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
> > > > @@ -184,6 +184,17 @@ scif: serial@11c01400 {
> > > >                       status = "disabled";
> > > >               };
> > > >
> > > > +             wdt0: watchdog@11c00400 {
> > > > +                     compatible = "renesas,r9a09g057-wdt";
> > > > +                     reg = <0 0x11c00400 0 0x400>;
> > > > +                     clocks = <&cpg CPG_MOD 75>,
> > > > +                              <&cpg CPG_MOD 76>;
> > > > +                     clock-names = "pclk", "oscclk";
> > > > +                     resets = <&cpg 117>;
> > > > +                     power-domains = <&cpg>;
> > > > +                     status = "disabled";
> > > > +             };
> > > > +
> > > >               ostm4: timer@12c00000 {
> > > >                       compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
> > > >                       reg = <0x0 0x12c00000 0x0 0x1000>;
> > > > @@ -224,6 +235,28 @@ ostm7: timer@12c03000 {
> > > >                       status = "disabled";
> > > >               };
> > > >
> > > > +             wdt2: watchdog@13000000 {
> > > > +                     compatible = "renesas,r9a09g057-wdt";
> > > > +                     reg = <0 0x13000000 0 0x400>;
> > > > +                     clocks = <&cpg CPG_MOD 79>,
> > > > +                              <&cpg CPG_MOD 80>;
> > > > +                     clock-names = "pclk", "oscclk";
> > > > +                     resets = <&cpg 119>;
> > > > +                     power-domains = <&cpg>;
> > > > +                     status = "disabled";
> > > > +             };
> > >
> > > I guess same group(all wdt together) arranged together?? Not sure.
> > >
> > I think Geert prefers it to be sorted based on unit address. So I'll
> > let Geert make a decision on this (and the rest of the similar patches
> > where nodes are sorted based on unit address and not grouped based on
> > IP).
>
> Sorted based on unit-address, but keep all nodes of the same type together.
> I.e.:
>     wdt0: watchdog@11c00400 { ... };
>     wdt2: watchdog@13000000 { ... };
>     wdt3: watchdog@13000400 { ... };
>     wdt1: watchdog@14400000 { ... };
>
Got you, I will update the patches with above sorting and send a v3.

Cheers,
Prabhakar
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
index 435b1f4e7d38..7f4e8ad9b0a5 100644
--- a/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a09g057.dtsi
@@ -184,6 +184,17 @@  scif: serial@11c01400 {
 			status = "disabled";
 		};
 
+		wdt0: watchdog@11c00400 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x11c00400 0 0x400>;
+			clocks = <&cpg CPG_MOD 75>,
+				 <&cpg CPG_MOD 76>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 117>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		ostm4: timer@12c00000 {
 			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
 			reg = <0x0 0x12c00000 0x0 0x1000>;
@@ -224,6 +235,28 @@  ostm7: timer@12c03000 {
 			status = "disabled";
 		};
 
+		wdt2: watchdog@13000000 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x13000000 0 0x400>;
+			clocks = <&cpg CPG_MOD 79>,
+				 <&cpg CPG_MOD 80>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 119>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
+		wdt3: watchdog@13000400 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x13000400 0 0x400>;
+			clocks = <&cpg CPG_MOD 81>,
+				 <&cpg CPG_MOD 82>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 120>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		ostm2: timer@14000000 {
 			compatible = "renesas,r9a09g057-ostm", "renesas,ostm";
 			reg = <0x0 0x14000000 0x0 0x1000>;
@@ -244,6 +277,17 @@  ostm3: timer@14001000 {
 			status = "disabled";
 		};
 
+		wdt1: watchdog@14400000 {
+			compatible = "renesas,r9a09g057-wdt";
+			reg = <0 0x14400000 0 0x400>;
+			clocks = <&cpg CPG_MOD 77>,
+				 <&cpg CPG_MOD 78>;
+			clock-names = "pclk", "oscclk";
+			resets = <&cpg 118>;
+			power-domains = <&cpg>;
+			status = "disabled";
+		};
+
 		i2c0: i2c@14400400 {
 			#address-cells = <1>;
 			#size-cells = <0>;