| Message ID | 20240703022732.2068316-1-ruanjinjie@huawei.com (mailing list archive) |
|---|---|
| State | Accepted |
| Commit | 63dd775cc05097e34192e3748849e72fdaf3b393 |
| Headers | show |
| Series | [RFC] riscv: Enable generic CPU vulnerabilites support | expand |
On Tue, 02 Jul 2024 19:27:32 PDT (-0700), ruanjinjie@huawei.com wrote: > Currently x86, ARM and ARM64 support generic CPU vulnerabilites, but > RISC-V not, such as: > > # cd /sys/devices/system/cpu/vulnerabilities/ > x86: > # cat spec_store_bypass > Mitigation: Speculative Store Bypass disabled via prctl and seccomp > # cat meltdown > Not affected > > ARM64: > > # cat spec_store_bypass > Mitigation: Speculative Store Bypass disabled via prctl and seccomp > # cat meltdown > Mitigation: PTI > > RISC-V: > > # cat /sys/devices/system/cpu/vulnerabilities > # ... No such file or directory > > As SiFive RISC-V Core IP offerings are not affected by Meltdown and > Spectre, it can use the default weak function as below: > > # cat spec_store_bypass > Not affected > # cat meltdown > Not affected > > Link: https://www.sifive.cn/blog/sifive-statement-on-meltdown-and-spectre > > Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> > --- > arch/riscv/Kconfig | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig > index 0525ee2d63c7..3b44e7b51436 100644 > --- a/arch/riscv/Kconfig > +++ b/arch/riscv/Kconfig > @@ -85,6 +85,7 @@ config RISCV > select GENERIC_ATOMIC64 if !64BIT > select GENERIC_CLOCKEVENTS_BROADCAST if SMP > select GENERIC_CPU_DEVICES > + select GENERIC_CPU_VULNERABILITIES > select GENERIC_EARLY_IOREMAP > select GENERIC_ENTRY > select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO Thanks. This is an RFC, but I'm just going to pick it up on for-next: we had a recent round of RISC-V vulnerabilities crop up, so it's time to start tracking those for users. It's queued up for now, it'll show up on for-next proper assumin it passes the tests. Thanks!
Hello: This patch was applied to riscv/linux.git (for-next) by Palmer Dabbelt <palmer@rivosinc.com>: On Wed, 3 Jul 2024 10:27:32 +0800 you wrote: > Currently x86, ARM and ARM64 support generic CPU vulnerabilites, but > RISC-V not, such as: > > # cd /sys/devices/system/cpu/vulnerabilities/ > x86: > # cat spec_store_bypass > Mitigation: Speculative Store Bypass disabled via prctl and seccomp > # cat meltdown > Not affected > > [...] Here is the summary with links: - [RFC] riscv: Enable generic CPU vulnerabilites support https://git.kernel.org/riscv/c/63dd775cc050 You are awesome, thank you!
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig index 0525ee2d63c7..3b44e7b51436 100644 --- a/arch/riscv/Kconfig +++ b/arch/riscv/Kconfig @@ -85,6 +85,7 @@ config RISCV select GENERIC_ATOMIC64 if !64BIT select GENERIC_CLOCKEVENTS_BROADCAST if SMP select GENERIC_CPU_DEVICES + select GENERIC_CPU_VULNERABILITIES select GENERIC_EARLY_IOREMAP select GENERIC_ENTRY select GENERIC_GETTIMEOFDAY if HAVE_GENERIC_VDSO
Currently x86, ARM and ARM64 support generic CPU vulnerabilites, but RISC-V not, such as: # cd /sys/devices/system/cpu/vulnerabilities/ x86: # cat spec_store_bypass Mitigation: Speculative Store Bypass disabled via prctl and seccomp # cat meltdown Not affected ARM64: # cat spec_store_bypass Mitigation: Speculative Store Bypass disabled via prctl and seccomp # cat meltdown Mitigation: PTI RISC-V: # cat /sys/devices/system/cpu/vulnerabilities # ... No such file or directory As SiFive RISC-V Core IP offerings are not affected by Meltdown and Spectre, it can use the default weak function as below: # cat spec_store_bypass Not affected # cat meltdown Not affected Link: https://www.sifive.cn/blog/sifive-statement-on-meltdown-and-spectre Signed-off-by: Jinjie Ruan <ruanjinjie@huawei.com> --- arch/riscv/Kconfig | 1 + 1 file changed, 1 insertion(+)