[0/2] More X1E bits

Message ID	20240716-topic-h_bits-v1-0-f6c5d3ff982c@linaro.org (mailing list archive)
Headers	show Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7A8D198E9F for <linux-arm-msm@vger.kernel.org>; Tue, 16 Jul 2024 10:35:08 +0000 (UTC) From: Konrad Dybcio <konrad.dybcio@linaro.org> Subject: [PATCH 0/2] More X1E bits Date: Tue, 16 Jul 2024 12:35:02 +0200 Message-Id: <20240716-topic-h_bits-v1-0-f6c5d3ff982c@linaro.org> Precedence: bulk MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit To: Bjorn Andersson <andersson@kernel.org>, Rob Herring <robh@kernel.org>, Krzysztof Kozlowski <krzk+dt@kernel.org>, Conor Dooley <conor+dt@kernel.org>, Akhil P Oommen <quic_akhilpo@quicinc.com>, Sibi Sankar <quic_sibis@quicinc.com>, Rajendra Nayak <quic_rjendra@quicinc.com>, Abel Vesa <abel.vesa@linaro.org> Cc: Marijn Suijten <marijn.suijten@somainline.org>, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio <konrad.dybcio@linaro.org>
Series	More X1E bits \| expand [0/2] More X1E bits [1/2] arm64: dts: qcom: x1e80100: Fix Adreno SMMU global interrupt [2/2] arm64: dts: qcom: x1e80100: Update C4/C5 residency/exit numbers

Message ID

20240716-topic-h_bits-v1-0-f6c5d3ff982c@linaro.org (mailing list archive)

Headers

From: Konrad Dybcio <konrad.dybcio@linaro.org>
Subject: [PATCH 0/2] More X1E bits
Date: Tue, 16 Jul 2024 12:35:02 +0200
Message-Id: <20240716-topic-h_bits-v1-0-f6c5d3ff982c@linaro.org>
Precedence: bulk
MIME-Version: 1.0
Content-Type: text/plain; charset="utf-8"
Content-Transfer-Encoding: 7bit
To: Bjorn Andersson <andersson@kernel.org>, Rob Herring <robh@kernel.org>,
 Krzysztof Kozlowski <krzk+dt@kernel.org>,
 Conor Dooley <conor+dt@kernel.org>,
 Akhil P Oommen <quic_akhilpo@quicinc.com>,
 Sibi Sankar <quic_sibis@quicinc.com>,
 Rajendra Nayak <quic_rjendra@quicinc.com>, Abel Vesa <abel.vesa@linaro.org>
Cc: Marijn Suijten <marijn.suijten@somainline.org>,
 linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org,
 linux-kernel@vger.kernel.org, Konrad Dybcio <konrad.dybcio@linaro.org>

Series

More X1E bits | expand

Message

Konrad Dybcio July 16, 2024, 10:35 a.m. UTC

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Konrad Dybcio (2):
      arm64: dts: qcom: x1e80100: Fix Adreno SMMU global interrupt
      arm64: dts: qcom: x1e80100: Update C4/C5 residency/exit numbers

 arch/arm64/boot/dts/qcom/x1e80100.dtsi | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
---
base-commit: 4f40be61af99a67d5580c1448acd9b74c0376389
change-id: 20240716-topic-h_bits-ef8b61485b5f

Best regards,

On Tue, 16 Jul 2024 12:35:02 +0200, Konrad Dybcio wrote: > Applied, thanks! [1/2] arm64: dts: qcom: x1e80100: Fix Adreno SMMU global interrupt commit: dfbe93f32c12f5628bd83303e10ba63621c259ae Best regards,

[0/2] More X1E bits

Message

Comments