diff mbox series

[03/12] drm/i915/dss: Move to struct intel_display

Message ID 20240826111527.1113622-4-ankit.k.nautiyal@intel.com (mailing list archive)
State New, archived
Headers show
Series Consolidation of DSS Control in Separate Files | expand

Commit Message

Nautiyal, Ankit K Aug. 26, 2024, 11:15 a.m. UTC 
Use struct intel_display instead of struct drm_i915_private.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c |  2 +-
 drivers/gpu/drm/i915/display/intel_dss.c | 22 +++++++++++-----------
 drivers/gpu/drm/i915/display/intel_dss.h |  4 ++--
 3 files changed, 14 insertions(+), 14 deletions(-)

Comments

Jani Nikula Aug. 26, 2024, 11:55 a.m. UTC | #1 
On Mon, 26 Aug 2024, Ankit Nautiyal <ankit.k.nautiyal@intel.com> wrote:
> Use struct intel_display instead of struct drm_i915_private.
>
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_ddi.c |  2 +-
>  drivers/gpu/drm/i915/display/intel_dss.c | 22 +++++++++++-----------
>  drivers/gpu/drm/i915/display/intel_dss.h |  4 ++--
>  3 files changed, 14 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
> index 28ef6814c56c..de7db5a028db 100644
> --- a/drivers/gpu/drm/i915/display/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/display/intel_ddi.c
> @@ -5115,7 +5115,7 @@ void intel_ddi_init(struct intel_display *display,
>  		dig_port->hpd_pulse = intel_dp_hpd_pulse;
>  
>  		if (dig_port->dp.mso_link_count)
> -			encoder->pipe_mask = intel_dss_splitter_pipe_mask(dev_priv);
> +			encoder->pipe_mask = intel_dss_splitter_pipe_mask(display);
>  	}
>  
>  	/*
> diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
> index 41ea42d234f9..9cb89fe656cb 100644
> --- a/drivers/gpu/drm/i915/display/intel_dss.c
> +++ b/drivers/gpu/drm/i915/display/intel_dss.c
> @@ -14,11 +14,11 @@
>   * Splitter enable for eDP MSO is limited to certain pipes, on certain
>   * platforms.
>   */
> -u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915)
> +u8 intel_dss_splitter_pipe_mask(struct intel_display *display)
>  {
> -	if (DISPLAY_VER(i915) > 20)
> +	if (DISPLAY_VER(display) > 20)
>  		return ~0;
> -	else if (IS_ALDERLAKE_P(i915))
> +	else if (IS_ALDERLAKE_P(to_i915(display->drm)))

I think it's easier for subsequent conversions to have i915 as a local
variable instead of adding to_i915() inline.

>  		return BIT(PIPE_A) | BIT(PIPE_B);
>  	else
>  		return BIT(PIPE_A);
> @@ -27,28 +27,28 @@ u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915)
>  void intel_dss_get_mso_config(struct intel_encoder *encoder,
>  			      struct intel_crtc_state *pipe_config)
>  {
> +	struct intel_display *display = to_intel_display(pipe_config);
>  	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	u32 dss1;
>  
> -	if (!HAS_MSO(i915))
> +	if (!HAS_MSO(display))
>  		return;
>  
> -	dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
> +	dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
>  
>  	pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
>  	if (!pipe_config->splitter.enable)
>  		return;
>  
> -	if (drm_WARN_ON(&i915->drm, !(intel_dss_splitter_pipe_mask(i915) & BIT(pipe)))) {
> +	if (drm_WARN_ON(crtc->base.dev, !(intel_dss_splitter_pipe_mask(display) & BIT(pipe)))) {

display->drm

>  		pipe_config->splitter.enable = false;
>  		return;
>  	}
>  
>  	switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
>  	default:
> -		drm_WARN(&i915->drm, true,
> +		drm_WARN(crtc->base.dev, true,

display->drm

>  			 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
>  		fallthrough;
>  	case SPLITTER_CONFIGURATION_2_SEGMENT:
> @@ -64,12 +64,12 @@ void intel_dss_get_mso_config(struct intel_encoder *encoder,
>  
>  void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state)
>  {
> +	struct intel_display *display = to_intel_display(crtc_state);
>  	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> -	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
>  	enum pipe pipe = crtc->pipe;
>  	u32 dss1 = 0;
>  
> -	if (!HAS_MSO(i915))
> +	if (!HAS_MSO(display))
>  		return;
>  
>  	if (crtc_state->splitter.enable) {
> @@ -81,7 +81,7 @@ void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state)
>  			dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
>  	}
>  
> -	intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
> +	intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe),
>  		     SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
>  		     OVERLAP_PIXELS_MASK, dss1);
>  }
> diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h
> index 632a00f0ebc1..0571ee2a19f9 100644
> --- a/drivers/gpu/drm/i915/display/intel_dss.h
> +++ b/drivers/gpu/drm/i915/display/intel_dss.h
> @@ -8,11 +8,11 @@
>  
>  #include "linux/types.h"
>  
> -struct drm_i915_private;
>  struct intel_crtc_state;
> +struct intel_display;
>  struct intel_encoder;
>  
> -u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915);
> +u8 intel_dss_splitter_pipe_mask(struct intel_display *display);
>  void intel_dss_get_mso_config(struct intel_encoder *encoder,
>  			      struct intel_crtc_state *pipe_config);
>  void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state);
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 28ef6814c56c..de7db5a028db 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -5115,7 +5115,7 @@  void intel_ddi_init(struct intel_display *display,
 		dig_port->hpd_pulse = intel_dp_hpd_pulse;
 
 		if (dig_port->dp.mso_link_count)
-			encoder->pipe_mask = intel_dss_splitter_pipe_mask(dev_priv);
+			encoder->pipe_mask = intel_dss_splitter_pipe_mask(display);
 	}
 
 	/*
diff --git a/drivers/gpu/drm/i915/display/intel_dss.c b/drivers/gpu/drm/i915/display/intel_dss.c
index 41ea42d234f9..9cb89fe656cb 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.c
+++ b/drivers/gpu/drm/i915/display/intel_dss.c
@@ -14,11 +14,11 @@ 
  * Splitter enable for eDP MSO is limited to certain pipes, on certain
  * platforms.
  */
-u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915)
+u8 intel_dss_splitter_pipe_mask(struct intel_display *display)
 {
-	if (DISPLAY_VER(i915) > 20)
+	if (DISPLAY_VER(display) > 20)
 		return ~0;
-	else if (IS_ALDERLAKE_P(i915))
+	else if (IS_ALDERLAKE_P(to_i915(display->drm)))
 		return BIT(PIPE_A) | BIT(PIPE_B);
 	else
 		return BIT(PIPE_A);
@@ -27,28 +27,28 @@  u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915)
 void intel_dss_get_mso_config(struct intel_encoder *encoder,
 			      struct intel_crtc_state *pipe_config)
 {
+	struct intel_display *display = to_intel_display(pipe_config);
 	struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	u32 dss1;
 
-	if (!HAS_MSO(i915))
+	if (!HAS_MSO(display))
 		return;
 
-	dss1 = intel_de_read(i915, ICL_PIPE_DSS_CTL1(pipe));
+	dss1 = intel_de_read(display, ICL_PIPE_DSS_CTL1(pipe));
 
 	pipe_config->splitter.enable = dss1 & SPLITTER_ENABLE;
 	if (!pipe_config->splitter.enable)
 		return;
 
-	if (drm_WARN_ON(&i915->drm, !(intel_dss_splitter_pipe_mask(i915) & BIT(pipe)))) {
+	if (drm_WARN_ON(crtc->base.dev, !(intel_dss_splitter_pipe_mask(display) & BIT(pipe)))) {
 		pipe_config->splitter.enable = false;
 		return;
 	}
 
 	switch (dss1 & SPLITTER_CONFIGURATION_MASK) {
 	default:
-		drm_WARN(&i915->drm, true,
+		drm_WARN(crtc->base.dev, true,
 			 "Invalid splitter configuration, dss1=0x%08x\n", dss1);
 		fallthrough;
 	case SPLITTER_CONFIGURATION_2_SEGMENT:
@@ -64,12 +64,12 @@  void intel_dss_get_mso_config(struct intel_encoder *encoder,
 
 void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state)
 {
+	struct intel_display *display = to_intel_display(crtc_state);
 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
-	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
 	enum pipe pipe = crtc->pipe;
 	u32 dss1 = 0;
 
-	if (!HAS_MSO(i915))
+	if (!HAS_MSO(display))
 		return;
 
 	if (crtc_state->splitter.enable) {
@@ -81,7 +81,7 @@  void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state)
 			dss1 |= SPLITTER_CONFIGURATION_4_SEGMENT;
 	}
 
-	intel_de_rmw(i915, ICL_PIPE_DSS_CTL1(pipe),
+	intel_de_rmw(display, ICL_PIPE_DSS_CTL1(pipe),
 		     SPLITTER_ENABLE | SPLITTER_CONFIGURATION_MASK |
 		     OVERLAP_PIXELS_MASK, dss1);
 }
diff --git a/drivers/gpu/drm/i915/display/intel_dss.h b/drivers/gpu/drm/i915/display/intel_dss.h
index 632a00f0ebc1..0571ee2a19f9 100644
--- a/drivers/gpu/drm/i915/display/intel_dss.h
+++ b/drivers/gpu/drm/i915/display/intel_dss.h
@@ -8,11 +8,11 @@ 
 
 #include "linux/types.h"
 
-struct drm_i915_private;
 struct intel_crtc_state;
+struct intel_display;
 struct intel_encoder;
 
-u8 intel_dss_splitter_pipe_mask(struct drm_i915_private *i915);
+u8 intel_dss_splitter_pipe_mask(struct intel_display *display);
 void intel_dss_get_mso_config(struct intel_encoder *encoder,
 			      struct intel_crtc_state *pipe_config);
 void intel_dss_configure_mso(const struct intel_crtc_state *crtc_state);