| Message ID | 20240703145851.204306-2-biju.das.jz@bp.renesas.com (mailing list archive) |
|---|---|
| State | Superseded |
| Delegated to: | Geert Uytterhoeven |
| Headers | show |
| Series | Enable serial NOR flash on RZ/G2UL SMARC EVK | expand |
Hi Krzysztof Kozlowski, Michael, Gentle ping. Are you happy with this patch? or do you have different opinion? This patch is based on RFC discussion [1] [1] RFC: https://lore.kernel.org/all/c9b0cffbb1566a7d38f2251ac7c8883a@walle.cc/ Cheers, Biju > -----Original Message----- > From: Biju Das <biju.das.jz@bp.renesas.com> > Sent: Wednesday, July 3, 2024 3:59 PM > To: Krzysztof Kozlowski <krzk@kernel.org> > Cc: Biju Das <biju.das.jz@bp.renesas.com>; Geert Uytterhoeven <geert+renesas@glider.be>; Michael Walle > <michael@walle.cc>; Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>; biju.das.au > <biju.das.au@gmail.com>; linux-renesas-soc@vger.kernel.org > Subject: [PATCH 1/3] memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins > > The RZ/{G2L,G2LC,V2L} SMARC EVK uses Micron MT25QU412A flash and RZ/G2UL SMARC EVK uses Renesas > AT25QL128A flash. With current pin setting for IOVF pin, 4-bit flash write fails for AT25QL128A flash. > Use Hi-Z state as the default for IOVF pin, so that spi controller driver in linux will be independent > of flash type. > > To support this, during board production, the bit 4 of the NV config register must be cleared by the > bootloader for Micron flash. > > Output from u-boot after clearing bit4 of NVCR register. > => renesas_micron_flash_nvcr > SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB NVCR=0xef > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> > --- > RFC->v1: > * New patch. > --- > drivers/memory/renesas-rpc-if.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index > 3167826b236a..7fbd36fa1a1b 100644 > --- a/drivers/memory/renesas-rpc-if.c > +++ b/drivers/memory/renesas-rpc-if.c > @@ -367,7 +367,7 @@ int rpcif_hw_init(struct device *dev, bool hyperflash) > regmap_update_bits(rpc->regmap, RPCIF_CMNCR, > RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) | > RPCIF_CMNCR_BSZ(3), > - RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) | > + RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(3) | > RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); > else > regmap_update_bits(rpc->regmap, RPCIF_CMNCR, > -- > 2.43.0
On 28/08/2024 19:02, Biju Das wrote: > Hi Krzysztof Kozlowski, Michael, > > Gentle ping. Are you happy with this patch? or do you have different opinion? > > This patch is based on RFC discussion [1] > > [1] RFC: https://lore.kernel.org/all/c9b0cffbb1566a7d38f2251ac7c8883a@walle.cc/ sorry, I don't have this patch in the inbox (anything older than 1 month disappears). Even if it reached me, it was an reply to unrelated patchset, so it could have been applied. And probably - due to being inside other thread - got immediately discarded. Do not attach (thread) your patchsets to some other threads (unrelated or older versions). This buries them deep in the mailbox and might interfere with applying entire sets. Please resend. Best regards, Krzysztof
On 30/08/2024 12:46, Krzysztof Kozlowski wrote: > On 28/08/2024 19:02, Biju Das wrote: >> Hi Krzysztof Kozlowski, Michael, >> >> Gentle ping. Are you happy with this patch? or do you have different opinion? >> >> This patch is based on RFC discussion [1] >> >> [1] RFC: https://lore.kernel.org/all/c9b0cffbb1566a7d38f2251ac7c8883a@walle.cc/ > > sorry, I don't have this patch in the inbox (anything older than 1 month > disappears). Even if it reached me, it was an reply to unrelated > patchset, so it could have been applied. And probably - due to being "so it could have not been applied." > inside other thread - got immediately discarded. > > Do not attach (thread) your patchsets to some other threads (unrelated > or older versions). This buries them deep in the mailbox and might > interfere with applying entire sets. > > Please resend. Maybe the threading was correct, but I missed it because of my DT filters. I don't know. Sorry for that, please resend. Best regards, Krzysztof
Hi Krzysztof Kozlowski, Thanks for the feedback. > -----Original Message----- > From: Krzysztof Kozlowski <krzk@kernel.org> > Sent: Friday, August 30, 2024 11:50 AM > Subject: Re: [PATCH 1/3] memory: renesas-rpc-if: Use Hi-Z state as the default setting for IOVF pins > > On 30/08/2024 12:46, Krzysztof Kozlowski wrote: > > On 28/08/2024 19:02, Biju Das wrote: > >> Hi Krzysztof Kozlowski, Michael, > >> > >> Gentle ping. Are you happy with this patch? or do you have different opinion? > >> > >> This patch is based on RFC discussion [1] > >> > >> [1] RFC: > >> https://lore.kernel.org/all/c9b0cffbb1566a7d38f2251ac7c8883a@walle.cc > >> / > > > > sorry, I don't have this patch in the inbox (anything older than 1 > > month disappears). Even if it reached me, it was an reply to unrelated > > patchset, so it could have been applied. And probably - due to being > > "so it could have not been applied." > > > inside other thread - got immediately discarded. > > > > Do not attach (thread) your patchsets to some other threads (unrelated > > or older versions). This buries them deep in the mailbox and might > > interfere with applying entire sets. > > > > Please resend. > > Maybe the threading was correct, but I missed it because of my DT filters. I don't know. Sorry for > that, please resend. Sure. Will resend. Cheers, Biju
diff --git a/drivers/memory/renesas-rpc-if.c b/drivers/memory/renesas-rpc-if.c index 3167826b236a..7fbd36fa1a1b 100644 --- a/drivers/memory/renesas-rpc-if.c +++ b/drivers/memory/renesas-rpc-if.c @@ -367,7 +367,7 @@ int rpcif_hw_init(struct device *dev, bool hyperflash) regmap_update_bits(rpc->regmap, RPCIF_CMNCR, RPCIF_CMNCR_MOIIO(3) | RPCIF_CMNCR_IOFV(3) | RPCIF_CMNCR_BSZ(3), - RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(2) | + RPCIF_CMNCR_MOIIO(1) | RPCIF_CMNCR_IOFV(3) | RPCIF_CMNCR_BSZ(hyperflash ? 1 : 0)); else regmap_update_bits(rpc->regmap, RPCIF_CMNCR,
The RZ/{G2L,G2LC,V2L} SMARC EVK uses Micron MT25QU412A flash and RZ/G2UL SMARC EVK uses Renesas AT25QL128A flash. With current pin setting for IOVF pin, 4-bit flash write fails for AT25QL128A flash. Use Hi-Z state as the default for IOVF pin, so that spi controller driver in linux will be independent of flash type. To support this, during board production, the bit 4 of the NV config register must be cleared by the bootloader for Micron flash. Output from u-boot after clearing bit4 of NVCR register. => renesas_micron_flash_nvcr SF: Detected mt25qu512a with page size 256 Bytes, erase size 64 KiB, total 64 MiB NVCR=0xef Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> --- RFC->v1: * New patch. --- drivers/memory/renesas-rpc-if.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)