diff mbox series

[2/3] drivers/perf: hisi_pcie: Fix TLP headers bandwidth counting

Message ID 20240829090332.28756-3-yangyicong@huawei.com (mailing list archive)
State New, archived
Headers show
Series Some updates for HiSilicon PCIe PMU | expand

Commit Message

Yicong Yang Aug. 29, 2024, 9:03 a.m. UTC 
From: Yicong Yang <yangyicong@hisilicon.com>

We make the initial value of event ctrl register as HISI_PCIE_INIT_SET
and modify according to the user options. This will make TLP headers
bandwidth only counting never take effect since HISI_PCIE_INIT_SET
configures to count the TLP payloads bandwidth. Fix this by making
the initial value of event ctrl register as 0.

Fixes: 17d573984d4d ("drivers/perf: hisi: Add TLP filter support")
Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
---
 drivers/perf/hisilicon/hisi_pcie_pmu.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Jonathan Cameron Aug. 29, 2024, 1:42 p.m. UTC | #1 
On Thu, 29 Aug 2024 17:03:31 +0800
Yicong Yang <yangyicong@huawei.com> wrote:

> From: Yicong Yang <yangyicong@hisilicon.com>
> 
> We make the initial value of event ctrl register as HISI_PCIE_INIT_SET
> and modify according to the user options. This will make TLP headers
> bandwidth only counting never take effect since HISI_PCIE_INIT_SET
> configures to count the TLP payloads bandwidth. Fix this by making
> the initial value of event ctrl register as 0.
> 
> Fixes: 17d573984d4d ("drivers/perf: hisi: Add TLP filter support")
> Signed-off-by: Yicong Yang <yangyicong@hisilicon.com>
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
diff mbox series

Patch

diff --git a/drivers/perf/hisilicon/hisi_pcie_pmu.c b/drivers/perf/hisilicon/hisi_pcie_pmu.c
index fba569a8640c..f7d6c59d9930 100644
--- a/drivers/perf/hisilicon/hisi_pcie_pmu.c
+++ b/drivers/perf/hisilicon/hisi_pcie_pmu.c
@@ -208,7 +208,7 @@  static void hisi_pcie_pmu_writeq(struct hisi_pcie_pmu *pcie_pmu, u32 reg_offset,
 static u64 hisi_pcie_pmu_get_event_ctrl_val(struct perf_event *event)
 {
 	u64 port, trig_len, thr_len, len_mode;
-	u64 reg = HISI_PCIE_INIT_SET;
+	u64 reg = 0;
 
 	/* Config HISI_PCIE_EVENT_CTRL according to event. */
 	reg |= FIELD_PREP(HISI_PCIE_EVENT_M, hisi_pcie_get_real_event(event));