| Message ID | 20240818172835.121757-1-krzysztof.kozlowski@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | dt-bindings: phy: socionext,uniphier: add top-level constraints | expand |
On Sun, 18 Aug 2024 19:28:35 +0200, Krzysztof Kozlowski wrote: > Properties with variable number of items per each device are expected to > have widest constraints in top-level "properties:" block and further > customized (narrowed) in "if:then:". Add missing top-level constraints > for clock-names and reset-names. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > .../bindings/phy/socionext,uniphier-ahci-phy.yaml | 8 ++++++-- > .../bindings/phy/socionext,uniphier-pcie-phy.yaml | 8 ++++++-- > .../bindings/phy/socionext,uniphier-usb3hs-phy.yaml | 7 +++++-- > .../bindings/phy/socionext,uniphier-usb3ss-phy.yaml | 7 +++++-- > 4 files changed, 22 insertions(+), 8 deletions(-) > Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Hi Krzysztof, I have one comment. On 2024/08/19 2:28, Krzysztof Kozlowski wrote: > Properties with variable number of items per each device are expected to > have widest constraints in top-level "properties:" block and further > customized (narrowed) in "if:then:". Add missing top-level constraints > for clock-names and reset-names. > > Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> > --- > .../bindings/phy/socionext,uniphier-ahci-phy.yaml | 8 ++++++-- > .../bindings/phy/socionext,uniphier-pcie-phy.yaml | 8 ++++++-- > .../bindings/phy/socionext,uniphier-usb3hs-phy.yaml | 7 +++++-- > .../bindings/phy/socionext,uniphier-usb3ss-phy.yaml | 7 +++++-- > 4 files changed, 22 insertions(+), 8 deletions(-) > > diff --git > a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml > b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml > index de3cffc850bc..e34b875a1bb8 100644 > --- > a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml > +++ > b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml > @@ -30,13 +30,17 @@ properties: > minItems: 1 > maxItems: 2 > > - clock-names: true > + clock-names: > + minItems: 1 > + maxItems: 6 The maxItems of clocks is 2, so it should be 2. > > resets: > minItems: 2 > maxItems: 6 > > - reset-names: true > + reset-names: > + minItems: 2 > + maxItems: 6 > > allOf: > - if: > diff --git > a/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml > b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml > index b3ed2f74a414..9fc0e87c508e 100644 > --- > a/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml > +++ > b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml > @@ -31,13 +31,17 @@ properties: > minItems: 1 > maxItems: 2 > > - clock-names: true > + clock-names: > + minItems: 1 > + maxItems: 2 > > resets: > minItems: 1 > maxItems: 2 > > - reset-names: true > + reset-names: > + minItems: 1 > + maxItems: 2 > > socionext,syscon: > $ref: /schemas/types.yaml#/definitions/phandle > diff --git > a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml > b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml > index 2107d98ace15..25c4159f86e4 100644 > --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy. > yaml > +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy. > yaml > @@ -34,12 +34,15 @@ properties: > minItems: 2 > maxItems: 3 > > - clock-names: true > + clock-names: > + minItems: 2 > + maxItems: 3 > > resets: > maxItems: 2 > > - reset-names: true > + reset-names: > + maxItems: 2 > > vbus-supply: > description: A phandle to the regulator for USB VBUS > diff --git > a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml > b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml > index 8f5aa6238bf3..1f663e9901da 100644 > --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy. > yaml > +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy. > yaml > @@ -35,12 +35,15 @@ properties: > minItems: 2 > maxItems: 3 > > - clock-names: true > + clock-names: > + minItems: 2 > + maxItems: 3 > > resets: > maxItems: 2 > > - reset-names: true > + reset-names: > + maxItems: 2 > > vbus-supply: > description: A phandle to the regulator for USB VBUS, only for USB > host Other than that: Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> I'd appreciate if it could be applied in devicetree or phy. Thank you, --- Best Regards Kunihiko Hayashi
On Sun, 18 Aug 2024 19:28:35 +0200, Krzysztof Kozlowski wrote: > Properties with variable number of items per each device are expected to > have widest constraints in top-level "properties:" block and further > customized (narrowed) in "if:then:". Add missing top-level constraints > for clock-names and reset-names. > > Applied, thanks! [1/1] dt-bindings: phy: socionext,uniphier: add top-level constraints commit: 45a4237b9be24d6c93db9da2b2180810c5bb2929 Best regards,
diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml index de3cffc850bc..e34b875a1bb8 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-ahci-phy.yaml @@ -30,13 +30,17 @@ properties: minItems: 1 maxItems: 2 - clock-names: true + clock-names: + minItems: 1 + maxItems: 6 resets: minItems: 2 maxItems: 6 - reset-names: true + reset-names: + minItems: 2 + maxItems: 6 allOf: - if: diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml index b3ed2f74a414..9fc0e87c508e 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-pcie-phy.yaml @@ -31,13 +31,17 @@ properties: minItems: 1 maxItems: 2 - clock-names: true + clock-names: + minItems: 1 + maxItems: 2 resets: minItems: 1 maxItems: 2 - reset-names: true + reset-names: + minItems: 1 + maxItems: 2 socionext,syscon: $ref: /schemas/types.yaml#/definitions/phandle diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml index 2107d98ace15..25c4159f86e4 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3hs-phy.yaml @@ -34,12 +34,15 @@ properties: minItems: 2 maxItems: 3 - clock-names: true + clock-names: + minItems: 2 + maxItems: 3 resets: maxItems: 2 - reset-names: true + reset-names: + maxItems: 2 vbus-supply: description: A phandle to the regulator for USB VBUS diff --git a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml index 8f5aa6238bf3..1f663e9901da 100644 --- a/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml +++ b/Documentation/devicetree/bindings/phy/socionext,uniphier-usb3ss-phy.yaml @@ -35,12 +35,15 @@ properties: minItems: 2 maxItems: 3 - clock-names: true + clock-names: + minItems: 2 + maxItems: 3 resets: maxItems: 2 - reset-names: true + reset-names: + maxItems: 2 vbus-supply: description: A phandle to the regulator for USB VBUS, only for USB host
Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clock-names and reset-names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> --- .../bindings/phy/socionext,uniphier-ahci-phy.yaml | 8 ++++++-- .../bindings/phy/socionext,uniphier-pcie-phy.yaml | 8 ++++++-- .../bindings/phy/socionext,uniphier-usb3hs-phy.yaml | 7 +++++-- .../bindings/phy/socionext,uniphier-usb3ss-phy.yaml | 7 +++++-- 4 files changed, 22 insertions(+), 8 deletions(-)