@@ -22,7 +22,7 @@ typedef uint16_t __be16;
typedef uint32_t __be32;
typedef uint64_t __be64;
-#define __attribute_const__
+#define attr_const
#define __force
#define always_inline
#define noinline
@@ -44,25 +44,25 @@ struct arm64_ftr_bits {
s64 safe_val; /* safe value for FTR_EXACT features */
};
-static inline int __attribute_const__
+static inline int attr_const
cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
{
return (s64)(features << (64 - width - field)) >> (64 - width);
}
-static inline int __attribute_const__
+static inline int attr_const
cpuid_feature_extract_signed_field(u64 features, int field)
{
return cpuid_feature_extract_signed_field_width(features, field, 4);
}
-static inline unsigned int __attribute_const__
+static inline unsigned int attr_const
cpuid_feature_extract_unsigned_field_width(u64 features, int field, int width)
{
return (u64)(features << (64 - width - field)) >> (64 - width);
}
-static inline unsigned int __attribute_const__
+static inline unsigned int attr_const
cpuid_feature_extract_unsigned_field(u64 features, int field)
{
return cpuid_feature_extract_unsigned_field_width(features, field, 4);
@@ -73,7 +73,7 @@ static inline u64 arm64_ftr_mask(const struct arm64_ftr_bits *ftrp)
return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
}
-static inline int __attribute_const__
+static inline int attr_const
cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
{
return (sign) ?
@@ -81,7 +81,7 @@ cpuid_feature_extract_field_width(u64 features, int field, int width, bool sign)
cpuid_feature_extract_unsigned_field_width(features, field, width);
}
-static inline int __attribute_const__
+static inline int attr_const
cpuid_feature_extract_field(u64 features, int field, bool sign)
{
return cpuid_feature_extract_field_width(features, field, 4, sign);
@@ -4,13 +4,13 @@
#include <xen/types.h>
#include <xen/compiler.h>
-static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
+static inline attr_const __u32 ___arch__swab32(__u32 x)
{
asm("bswap %0" : "=r" (x) : "0" (x));
return x;
}
-static inline __attribute_const__ __u64 ___arch__swab64(__u64 val)
+static inline attr_const __u64 ___arch__swab64(__u64 val)
{
union {
struct { __u32 a,b; } s;
@@ -19,7 +19,7 @@
* gen_endbr64() is written deliberately to avoid the problematic operand, and
* marked __const__ as it is safe for the optimiser to hoist/merge/etc.
*/
-static inline uint32_t __attribute_const__ gen_endbr64(void)
+static inline uint32_t attr_const gen_endbr64(void)
{
uint32_t res;
@@ -45,7 +45,7 @@ static inline void place_endbr64(void *ptr)
* contain an ENDBR64 instruction. Use an encoding which isn't the default
* P6_NOP4. Specifically, nopw (%rcx)
*/
-static inline uint32_t __attribute_const__ gen_endbr64_poison(void)
+static inline uint32_t attr_const gen_endbr64_poison(void)
{
uint32_t res;
@@ -123,7 +123,7 @@
#endif /* OPTIMIZE */
-static inline __attribute_const__ __u16 __fswab16(__u16 x)
+static inline attr_const __u16 __fswab16(__u16 x)
{
return __arch__swab16(x);
}
@@ -136,7 +136,7 @@ static inline void __swab16s(__u16 *addr)
__arch__swab16s(addr);
}
-static inline __attribute_const__ __u32 __fswab32(__u32 x)
+static inline attr_const __u32 __fswab32(__u32 x)
{
return __arch__swab32(x);
}
@@ -150,7 +150,7 @@ static inline void __swab32s(__u32 *addr)
}
#ifdef __BYTEORDER_HAS_U64__
-static inline __attribute_const__ __u64 __fswab64(__u64 x)
+static inline attr_const __u64 __fswab64(__u64 x)
{
# ifdef __SWAB_64_THRU_32__
__u32 h = x >> 32;
@@ -88,7 +88,7 @@
#define __constructor __attribute__((__constructor__)) cf_check
#define __pure __attribute__((__pure__))
-#define __attribute_const__ __attribute__((__const__))
+#define attr_const __attribute__((__const__))
#define __transparent__ __attribute__((__transparent_union__))
/*
There's no need for the name to be so verbose. No functional change. Suggest-by: Jan Beulich <JBeulich@suse.com> Signed-off-by: Andrew Cooper <andrew.cooper3@citrix.com> --- CC: Jan Beulich <JBeulich@suse.com> CC: Roger Pau Monné <roger.pau@citrix.com> CC: Stefano Stabellini <sstabellini@kernel.org> CC: Julien Grall <julien@xen.org> CC: Volodymyr Babchuk <Volodymyr_Babchuk@epam.com> CC: Bertrand Marquis <bertrand.marquis@arm.com> CC: Michal Orzel <michal.orzel@amd.com> CC: Oleksii Kurochko <oleksii.kurochko@gmail.com> CC: Shawn Anastasio <sanastasio@raptorengineering.com> v2: * New --- tools/libs/guest/xg_dom_decompress_unsafe_zstd.c | 2 +- xen/arch/arm/include/asm/arm64/cpufeature.h | 12 ++++++------ xen/arch/x86/include/asm/byteorder.h | 4 ++-- xen/arch/x86/include/asm/endbr.h | 4 ++-- xen/include/xen/byteorder/swab.h | 6 +++--- xen/include/xen/compiler.h | 2 +- 6 files changed, 15 insertions(+), 15 deletions(-)