diff mbox series

[06/13] drm/i915/vrr: Compute vrr vsync if platforms support it

Message ID 20240902080635.2946858-7-ankit.k.nautiyal@intel.com (mailing list archive)
State New, archived
Headers show
Series Use VRR timing generator for fixed refresh rate modes | expand

Commit Message

Nautiyal, Ankit K Sept. 2, 2024, 8:06 a.m. UTC
Previously, TRANS_VRR_VSYNC was exclusively used for panels with
adaptive-sync SDP support in VRR scenarios. However, to drive fixed refresh
rates using the VRR Timing generator, we now need to program
TRANS_VRR_VSYNC regardless of adaptive sync SDP support. Therefore, let's
remove the adaptive sync SDP check and program TRANS_VRR_VSYNC for
platforms where VRR timing generator is used.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
---
 drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Comments

Ville Syrjälä Sept. 3, 2024, 12:45 p.m. UTC | #1
On Mon, Sep 02, 2024 at 01:36:27PM +0530, Ankit Nautiyal wrote:
> Previously, TRANS_VRR_VSYNC was exclusively used for panels with
> adaptive-sync SDP support in VRR scenarios. However, to drive fixed refresh
> rates using the VRR Timing generator, we now need to program
> TRANS_VRR_VSYNC regardless of adaptive sync SDP support. Therefore, let's
> remove the adaptive sync SDP check and program TRANS_VRR_VSYNC for
> platforms where VRR timing generator is used.
> 
> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
> index 9a51f5bac307..03af50b9f9eb 100644
> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
> @@ -231,7 +231,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>  		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>  	}
>  
> -	if (intel_dp->as_sdp_supported && crtc_state->vrr.enable) {
> +	if (HAS_AS_SDP(display) && crtc_state->vrr.enable) {

That vrr.enable check should be nuked as well. We are supposed to
compute the full state whether VRR is actually enabled or not.

>  		crtc_state->vrr.vsync_start =
>  			(crtc_state->hw.adjusted_mode.crtc_vtotal -
>  			 crtc_state->hw.adjusted_mode.vsync_start);
> -- 
> 2.45.2
Nautiyal, Ankit K Sept. 4, 2024, 12:55 p.m. UTC | #2
On 9/3/2024 6:15 PM, Ville Syrjälä wrote:
> On Mon, Sep 02, 2024 at 01:36:27PM +0530, Ankit Nautiyal wrote:
>> Previously, TRANS_VRR_VSYNC was exclusively used for panels with
>> adaptive-sync SDP support in VRR scenarios. However, to drive fixed refresh
>> rates using the VRR Timing generator, we now need to program
>> TRANS_VRR_VSYNC regardless of adaptive sync SDP support. Therefore, let's
>> remove the adaptive sync SDP check and program TRANS_VRR_VSYNC for
>> platforms where VRR timing generator is used.
>>
>> Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
>> ---
>>   drivers/gpu/drm/i915/display/intel_vrr.c | 2 +-
>>   1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
>> index 9a51f5bac307..03af50b9f9eb 100644
>> --- a/drivers/gpu/drm/i915/display/intel_vrr.c
>> +++ b/drivers/gpu/drm/i915/display/intel_vrr.c
>> @@ -231,7 +231,7 @@ intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
>>   		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
>>   	}
>>   
>> -	if (intel_dp->as_sdp_supported && crtc_state->vrr.enable) {
>> +	if (HAS_AS_SDP(display) && crtc_state->vrr.enable) {
> That vrr.enable check should be nuked as well. We are supposed to
> compute the full state whether VRR is actually enabled or not.

Hmm. We are trying to move to VRR TG from LNL+ so for these platform 
vrr.enable will always be set.
For older platforms where vrr.enable is not set, whether enabling 
TRANS_VRR_VSYNC can cause any issue?
If this is set and TRANS_VRR_CTL is disable, then perhaps it wont have 
any effect.

Regards,

Ankit


>
>>   		crtc_state->vrr.vsync_start =
>>   			(crtc_state->hw.adjusted_mode.crtc_vtotal -
>>   			 crtc_state->hw.adjusted_mode.vsync_start);
>> -- 
>> 2.45.2
diff mbox series

Patch

diff --git a/drivers/gpu/drm/i915/display/intel_vrr.c b/drivers/gpu/drm/i915/display/intel_vrr.c
index 9a51f5bac307..03af50b9f9eb 100644
--- a/drivers/gpu/drm/i915/display/intel_vrr.c
+++ b/drivers/gpu/drm/i915/display/intel_vrr.c
@@ -231,7 +231,7 @@  intel_vrr_compute_config(struct intel_crtc_state *crtc_state,
 		crtc_state->mode_flags |= I915_MODE_FLAG_VRR;
 	}
 
-	if (intel_dp->as_sdp_supported && crtc_state->vrr.enable) {
+	if (HAS_AS_SDP(display) && crtc_state->vrr.enable) {
 		crtc_state->vrr.vsync_start =
 			(crtc_state->hw.adjusted_mode.crtc_vtotal -
 			 crtc_state->hw.adjusted_mode.vsync_start);