| Message ID | 20240909085610.46625-2-ajones@ventanamicro.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | irqchip/riscv-imsic: Fix output text of base address | expand |
On Mon, Sep 9, 2024 at 2:26 PM Andrew Jones <ajones@ventanamicro.com> wrote: > > The "per-CPU IDs ... at base ..." info log is outputting a physical > address, not a PPN. > > Fixes: 027e125acdba ("irqchip/riscv-imsic: Add device MSI domain support for platform devices") > Signed-off-by: Andrew Jones <ajones@ventanamicro.com> LGTM. Reviewed-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > drivers/irqchip/irq-riscv-imsic-platform.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c > index 11723a763c10..c5ec66e0bfd3 100644 > --- a/drivers/irqchip/irq-riscv-imsic-platform.c > +++ b/drivers/irqchip/irq-riscv-imsic-platform.c > @@ -340,7 +340,7 @@ int imsic_irqdomain_init(void) > imsic->fwnode, global->hart_index_bits, global->guest_index_bits); > pr_info("%pfwP: group-index-bits: %d, group-index-shift: %d\n", > imsic->fwnode, global->group_index_bits, global->group_index_shift); > - pr_info("%pfwP: per-CPU IDs %d at base PPN %pa\n", > + pr_info("%pfwP: per-CPU IDs %d at base address %pa\n", > imsic->fwnode, global->nr_ids, &global->base_addr); > pr_info("%pfwP: total %d interrupts available\n", > imsic->fwnode, num_possible_cpus() * (global->nr_ids - 1)); > -- > 2.46.0 >
diff --git a/drivers/irqchip/irq-riscv-imsic-platform.c b/drivers/irqchip/irq-riscv-imsic-platform.c index 11723a763c10..c5ec66e0bfd3 100644 --- a/drivers/irqchip/irq-riscv-imsic-platform.c +++ b/drivers/irqchip/irq-riscv-imsic-platform.c @@ -340,7 +340,7 @@ int imsic_irqdomain_init(void) imsic->fwnode, global->hart_index_bits, global->guest_index_bits); pr_info("%pfwP: group-index-bits: %d, group-index-shift: %d\n", imsic->fwnode, global->group_index_bits, global->group_index_shift); - pr_info("%pfwP: per-CPU IDs %d at base PPN %pa\n", + pr_info("%pfwP: per-CPU IDs %d at base address %pa\n", imsic->fwnode, global->nr_ids, &global->base_addr); pr_info("%pfwP: total %d interrupts available\n", imsic->fwnode, num_possible_cpus() * (global->nr_ids - 1));
The "per-CPU IDs ... at base ..." info log is outputting a physical address, not a PPN. Fixes: 027e125acdba ("irqchip/riscv-imsic: Add device MSI domain support for platform devices") Signed-off-by: Andrew Jones <ajones@ventanamicro.com> --- drivers/irqchip/irq-riscv-imsic-platform.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)