| Message ID | 20231217210629.131486-4-bigunclemax@gmail.com (mailing list archive) |
|---|---|
| State | Handled Elsewhere |
| Delegated to: | Conor Dooley |
| Headers | show |
| Series | Add D1/T113s thermal sensor controller support | expand |
On Mon, 18 Dec 2023 00:06:24 +0300 Maksim Kiselev <bigunclemax@gmail.com> wrote: Hi, > From: Maxim Kiselev <bigunclemax@gmail.com> > > This patch adds a thermal sensor controller node for the D1/T113s. > Also it adds a THS calibration data cell to efuse node. > > Signed-off-by: Maxim Kiselev <bigunclemax@gmail.com> > --- > .../boot/dts/allwinner/sunxi-d1s-t113.dtsi | 17 +++++++++++++++++ > 1 file changed, 17 insertions(+) > > diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > index 5a9d7f5a75b4..6f5427d9cfbf 100644 > --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi > @@ -166,6 +166,19 @@ gpadc: adc@2009000 { > #io-channel-cells = <1>; > }; > > + ths: thermal-sensor@2009400 { > + compatible = "allwinner,sun20i-d1-ths"; > + reg = <0x02009400 0x400>; > + interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_THS>; > + clock-names = "bus"; > + resets = <&ccu RST_BUS_THS>; > + nvmem-cells = <&ths_calibration>; > + nvmem-cell-names = "calibration"; > + status = "disabled"; Any reason this is disabled? We typically don't disable those internal devices in the SoC .dtsi, the THS is one example (check the instances in other SoCs' .dtsi files). The rest looks alright, compared to the manual, so with this line removed: Reviewed-by: Andre Przywara <andre.przywara@arm.com> Cheers, Andre > + #thermal-sensor-cells = <0>; > + }; > + > dmic: dmic@2031000 { > compatible = "allwinner,sun20i-d1-dmic", > "allwinner,sun50i-h6-dmic"; > @@ -415,6 +428,10 @@ sid: efuse@3006000 { > reg = <0x3006000 0x1000>; > #address-cells = <1>; > #size-cells = <1>; > + > + ths_calibration: thermal-sensor-calibration@14 { > + reg = <0x14 0x4>; > + }; > }; > > crypto: crypto@3040000 {
Hi Maksim, Apologies if I have failed to find a v7 of this patch in my searching, but I'm seeing that patch #3 here was never applied, so Linux still does not enable the thermal sensor in these chips. I just thought I'd give you a heads-up in case you weren't aware. :) Thanks for all your hard work, Sam
On Mon, 9 Sep 2024 10:16:56 -0700 Sam Edwards <cfsworks@gmail.com> wrote: Hi, > Hi Maksim, > > Apologies if I have failed to find a v7 of this patch in my searching, > but I'm seeing that patch #3 here was never applied, so Linux still does > not enable the thermal sensor in these chips. I just thought I'd give > you a heads-up in case you weren't aware. :) There is an unaddressed comment on this patch: to remove the "disabled" status line. Sam, feel free to fix this and send the patch again, unless Maksim beats you to it. Cheers, Andre > > Thanks for all your hard work, > Sam >
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi index 5a9d7f5a75b4..6f5427d9cfbf 100644 --- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi +++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi @@ -166,6 +166,19 @@ gpadc: adc@2009000 { #io-channel-cells = <1>; }; + ths: thermal-sensor@2009400 { + compatible = "allwinner,sun20i-d1-ths"; + reg = <0x02009400 0x400>; + interrupts = <SOC_PERIPHERAL_IRQ(58) IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_THS>; + clock-names = "bus"; + resets = <&ccu RST_BUS_THS>; + nvmem-cells = <&ths_calibration>; + nvmem-cell-names = "calibration"; + status = "disabled"; + #thermal-sensor-cells = <0>; + }; + dmic: dmic@2031000 { compatible = "allwinner,sun20i-d1-dmic", "allwinner,sun50i-h6-dmic"; @@ -415,6 +428,10 @@ sid: efuse@3006000 { reg = <0x3006000 0x1000>; #address-cells = <1>; #size-cells = <1>; + + ths_calibration: thermal-sensor-calibration@14 { + reg = <0x14 0x4>; + }; }; crypto: crypto@3040000 {