| Message ID | 3A31C289BC240955+20240912025539.1928223-1-wangyuli@uniontech.com (mailing list archive) |
|---|---|
| State | Superseded |
| Headers | show |
| Series | [6.6,v2,1/4] riscv: dts: starfive: add assigned-clock* to limit frquency | expand |
| Context | Check | Description |
|---|---|---|
| conchuod/vmtest-fixes-PR | fail | merge-conflict |
On Thu, Sep 12, 2024 at 10:55:05AM +0800, WangYuli wrote: > From: William Qiu <william.qiu@starfivetech.com> > > [ Upstream commit af571133f7ae028ec9b5fdab78f483af13bf28d3 ] > > In JH7110 SoC, we need to go by-pass mode, so we need add the > assigned-clock* properties to limit clock frquency. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: WangYuli <wangyuli@uniontech.com> > --- > .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) Please rework this series and send only what is needed here. thanks, greg k-h
Le 12/09/2024 à 04:55, WangYuli a écrit : > From: William Qiu <william.qiu@starfivetech.com> > > [ Upstream commit af571133f7ae028ec9b5fdab78f483af13bf28d3 ] > > In JH7110 SoC, we need to go by-pass mode, so we need add the > assigned-clock* properties to limit clock frquency. > > Signed-off-by: William Qiu <william.qiu@starfivetech.com> > Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: WangYuli <wangyuli@uniontech.com> > --- Hi, if/when resent, there is a typo in the subject: s/frquency/frequency/ CJ > .../riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > index 062b97c6e7df..4874e3bb42ab 100644 > --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi > @@ -204,6 +204,8 @@ &i2c6 { > > &mmc0 { > max-frequency = <100000000>; > + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; > + assigned-clock-rates = <50000000>; > bus-width = <8>; > cap-mmc-highspeed; > mmc-ddr-1_8v; > @@ -220,6 +222,8 @@ &mmc0 { > > &mmc1 { > max-frequency = <100000000>; > + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; > + assigned-clock-rates = <50000000>; > bus-width = <4>; > no-sdio; > no-mmc;
On 2024/9/13 20:42, Greg KH wrote:
> Please rework this series and send only what is needed here.
OK, just one.
Link:https://lore.kernel.org/all/247345579659D8F7+20240916034603.59120-1-wangyuli@uniontech.com/
Thanks,
Since this commit is already in 'linux/master', changing its title for the backport might just make things more confusing. Thanks, -- WangYuli
diff --git a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi index 062b97c6e7df..4874e3bb42ab 100644 --- a/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi +++ b/arch/riscv/boot/dts/starfive/jh7110-starfive-visionfive-2.dtsi @@ -204,6 +204,8 @@ &i2c6 { &mmc0 { max-frequency = <100000000>; + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO0_SDCARD>; + assigned-clock-rates = <50000000>; bus-width = <8>; cap-mmc-highspeed; mmc-ddr-1_8v; @@ -220,6 +222,8 @@ &mmc0 { &mmc1 { max-frequency = <100000000>; + assigned-clocks = <&syscrg JH7110_SYSCLK_SDIO1_SDCARD>; + assigned-clock-rates = <50000000>; bus-width = <4>; no-sdio; no-mmc;