diff mbox series

intel_iommu: Remove Transient Mapping (TM) field from second-level page-tables

Message ID 20240930065245.2993767-1-zhenzhong.duan@intel.com (mailing list archive)
State New, archived
Headers show
Series intel_iommu: Remove Transient Mapping (TM) field from second-level page-tables | expand

Commit Message

Duan, Zhenzhong Sept. 30, 2024, 6:52 a.m. UTC 
VT-d spec removed Transient Mapping (TM) field from second-level page-tables
and treat the field as Reserved(0) since revision 3.2. Update code to match
spec.

This doesn't impact function of vIOMMU as there was no logic to emulate
Transient Mapping.

Suggested-by: Yi Liu <yi.l.liu@intel.com>
Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
---
 hw/i386/intel_iommu_internal.h | 13 +++----------
 hw/i386/intel_iommu.c          | 11 +++--------
 2 files changed, 6 insertions(+), 18 deletions(-)

Comments

CLEMENT MATHIEU--DRIF Sept. 30, 2024, 9:11 a.m. UTC | #1 
LGTM

Thanks
cmd

> Caution: External email. Do not open attachments or click links, unless this email comes from a known sender and you know the content is safe.
> 
> 
> VT-d spec removed Transient Mapping (TM) field from second-level page-tables
> and treat the field as Reserved(0) since revision 3.2. Update code to match
> spec.
> 
> This doesn't impact function of vIOMMU as there was no logic to emulate
> Transient Mapping.
> 
> Suggested-by: Yi Liu <yi.l.liu@intel.com>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
>  hw/i386/intel_iommu_internal.h | 13 +++----------
>  hw/i386/intel_iommu.c          | 11 +++--------
>  2 files changed, 6 insertions(+), 18 deletions(-)
> 
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index 13d5d129ae..c818c819fe 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -412,9 +412,7 @@ typedef union VTDInvDesc VTDInvDesc;
>  /* Rsvd field masks for spte */
>  #define VTD_SPTE_SNP 0x800ULL
> 
> -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
> -        dt_supported ? \
> -        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
>          (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
>  #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
>          (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> @@ -423,13 +421,9 @@ typedef union VTDInvDesc VTDInvDesc;
>  #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
>          (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> 
> -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
> -        dt_supported ? \
> -        (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
>          (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
> -        dt_supported ? \
> -        (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
>          (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> 
>  /* Information about page-selective IOTLB invalidate */
> @@ -536,6 +530,5 @@ typedef struct VTDRootEntry VTDRootEntry;
>  #define VTD_SL_W                    (1ULL << 1)
>  #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
>  #define VTD_SL_IGN_COM              0xbff0000000000000ULL
> -#define VTD_SL_TM                   (1ULL << 62)
> 
>  #endif
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 08fe218935..eb5aa2b2d5 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -4111,8 +4111,6 @@ static void vtd_cap_init(IntelIOMMUState *s)
>   */
>  static void vtd_init(IntelIOMMUState *s)
>  {
> -    X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
> -
>      memset(s->csr, 0, DMAR_REG_SIZE);
>      memset(s->wmask, 0, DMAR_REG_SIZE);
>      memset(s->w1cmask, 0, DMAR_REG_SIZE);
> @@ -4137,16 +4135,13 @@ static void vtd_init(IntelIOMMUState *s)
>       * Rsvd field masks for spte
>       */
>      vtd_spte_rsvd[0] = ~0ULL;
> -    vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
> -                                                  x86_iommu->dt_supported);
> +    vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
>      vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
>      vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
>      vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
> 
> -    vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
> -                                                    x86_iommu->dt_supported);
> -    vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
> -                                                    x86_iommu->dt_supported);
> +    vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
> +    vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
> 
>      if (s->scalable_mode || s->snoop_control) {
>          vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
> --
> 2.34.1
> 
> 
>
Jason Wang Oct. 9, 2024, 8:23 a.m. UTC | #2 
On Mon, Sep 30, 2024 at 2:56 PM Zhenzhong Duan <zhenzhong.duan@intel.com> wrote:
>
> VT-d spec removed Transient Mapping (TM) field from second-level page-tables
> and treat the field as Reserved(0) since revision 3.2. Update code to match
> spec.

Some questions:

1) Is there a version register for vtd so driver can know? Otherwise
we may break migration compatibility silently.
2) Is there any user for that field in the past? If yes, we probably
need a new parameter for this.

Thanks

>
> This doesn't impact function of vIOMMU as there was no logic to emulate
> Transient Mapping.
>
> Suggested-by: Yi Liu <yi.l.liu@intel.com>
> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
> ---
>  hw/i386/intel_iommu_internal.h | 13 +++----------
>  hw/i386/intel_iommu.c          | 11 +++--------
>  2 files changed, 6 insertions(+), 18 deletions(-)
>
> diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
> index 13d5d129ae..c818c819fe 100644
> --- a/hw/i386/intel_iommu_internal.h
> +++ b/hw/i386/intel_iommu_internal.h
> @@ -412,9 +412,7 @@ typedef union VTDInvDesc VTDInvDesc;
>  /* Rsvd field masks for spte */
>  #define VTD_SPTE_SNP 0x800ULL
>
> -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
> -        dt_supported ? \
> -        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
>          (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
>  #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
>          (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> @@ -423,13 +421,9 @@ typedef union VTDInvDesc VTDInvDesc;
>  #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
>          (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
>
> -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
> -        dt_supported ? \
> -        (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
>          (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
> -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
> -        dt_supported ? \
> -        (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
> +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
>          (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
>
>  /* Information about page-selective IOTLB invalidate */
> @@ -536,6 +530,5 @@ typedef struct VTDRootEntry VTDRootEntry;
>  #define VTD_SL_W                    (1ULL << 1)
>  #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
>  #define VTD_SL_IGN_COM              0xbff0000000000000ULL
> -#define VTD_SL_TM                   (1ULL << 62)
>
>  #endif
> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
> index 08fe218935..eb5aa2b2d5 100644
> --- a/hw/i386/intel_iommu.c
> +++ b/hw/i386/intel_iommu.c
> @@ -4111,8 +4111,6 @@ static void vtd_cap_init(IntelIOMMUState *s)
>   */
>  static void vtd_init(IntelIOMMUState *s)
>  {
> -    X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
> -
>      memset(s->csr, 0, DMAR_REG_SIZE);
>      memset(s->wmask, 0, DMAR_REG_SIZE);
>      memset(s->w1cmask, 0, DMAR_REG_SIZE);
> @@ -4137,16 +4135,13 @@ static void vtd_init(IntelIOMMUState *s)
>       * Rsvd field masks for spte
>       */
>      vtd_spte_rsvd[0] = ~0ULL;
> -    vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
> -                                                  x86_iommu->dt_supported);
> +    vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
>      vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
>      vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
>      vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
>
> -    vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
> -                                                    x86_iommu->dt_supported);
> -    vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
> -                                                    x86_iommu->dt_supported);
> +    vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
> +    vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
>
>      if (s->scalable_mode || s->snoop_control) {
>          vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
> --
> 2.34.1
>
Duan, Zhenzhong Oct. 10, 2024, 5:38 a.m. UTC | #3 
>-----Original Message-----
>From: Jason Wang <jasowang@redhat.com>
>Subject: Re: [PATCH] intel_iommu: Remove Transient Mapping (TM) field
>from second-level page-tables
>
>On Mon, Sep 30, 2024 at 2:56 PM Zhenzhong Duan
><zhenzhong.duan@intel.com> wrote:
>>
>> VT-d spec removed Transient Mapping (TM) field from second-level page-
>tables
>> and treat the field as Reserved(0) since revision 3.2. Update code to match
>> spec.
>
>Some questions:
>
>1) Is there a version register for vtd so driver can know? Otherwise
>we may break migration compatibility silently.

We have a VERSION register, but it's unrelated to revision. Yi can fix me if I understand wrong.

Bit VTD_SL_TM is not emulated in vIOMMU but OS can set it, indeed a possibility to break migration.

>2) Is there any user for that field in the past?

To be honest, I don't know. Linux doesn't set it.

> If yes, we probably need a new parameter for this.

Will try, e.g., "x-stale-tm".

Thanks
Zhenzhong

>
>Thanks
>
>>
>> This doesn't impact function of vIOMMU as there was no logic to emulate
>> Transient Mapping.
>>
>> Suggested-by: Yi Liu <yi.l.liu@intel.com>
>> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com>
>> ---
>>  hw/i386/intel_iommu_internal.h | 13 +++----------
>>  hw/i386/intel_iommu.c          | 11 +++--------
>>  2 files changed, 6 insertions(+), 18 deletions(-)
>>
>> diff --git a/hw/i386/intel_iommu_internal.h
>b/hw/i386/intel_iommu_internal.h
>> index 13d5d129ae..c818c819fe 100644
>> --- a/hw/i386/intel_iommu_internal.h
>> +++ b/hw/i386/intel_iommu_internal.h
>> @@ -412,9 +412,7 @@ typedef union VTDInvDesc VTDInvDesc;
>>  /* Rsvd field masks for spte */
>>  #define VTD_SPTE_SNP 0x800ULL
>>
>> -#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
>> -        dt_supported ? \
>> -        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM |
>VTD_SL_TM)) : \
>> +#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
>>          (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
>>  #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
>>          (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
>> @@ -423,13 +421,9 @@ typedef union VTDInvDesc VTDInvDesc;
>>  #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
>>          (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
>>
>> -#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
>> -        dt_supported ? \
>> -        (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM |
>VTD_SL_TM)) : \
>> +#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
>>          (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
>> -#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
>> -        dt_supported ? \
>> -        (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM |
>VTD_SL_TM)) : \
>> +#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
>>          (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
>>
>>  /* Information about page-selective IOTLB invalidate */
>> @@ -536,6 +530,5 @@ typedef struct VTDRootEntry VTDRootEntry;
>>  #define VTD_SL_W                    (1ULL << 1)
>>  #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) &
>VTD_HAW_MASK(aw))
>>  #define VTD_SL_IGN_COM              0xbff0000000000000ULL
>> -#define VTD_SL_TM                   (1ULL << 62)
>>
>>  #endif
>> diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
>> index 08fe218935..eb5aa2b2d5 100644
>> --- a/hw/i386/intel_iommu.c
>> +++ b/hw/i386/intel_iommu.c
>> @@ -4111,8 +4111,6 @@ static void vtd_cap_init(IntelIOMMUState *s)
>>   */
>>  static void vtd_init(IntelIOMMUState *s)
>>  {
>> -    X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
>> -
>>      memset(s->csr, 0, DMAR_REG_SIZE);
>>      memset(s->wmask, 0, DMAR_REG_SIZE);
>>      memset(s->w1cmask, 0, DMAR_REG_SIZE);
>> @@ -4137,16 +4135,13 @@ static void vtd_init(IntelIOMMUState *s)
>>       * Rsvd field masks for spte
>>       */
>>      vtd_spte_rsvd[0] = ~0ULL;
>> -    vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
>> -                                                  x86_iommu->dt_supported);
>> +    vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
>>      vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
>>      vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
>>      vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
>>
>> -    vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s-
>>aw_bits,
>> -                                                    x86_iommu->dt_supported);
>> -    vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s-
>>aw_bits,
>> -                                                    x86_iommu->dt_supported);
>> +    vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s-
>>aw_bits);
>> +    vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s-
>>aw_bits);
>>
>>      if (s->scalable_mode || s->snoop_control) {
>>          vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;
>> --
>> 2.34.1
>>
diff mbox series

Patch

diff --git a/hw/i386/intel_iommu_internal.h b/hw/i386/intel_iommu_internal.h
index 13d5d129ae..c818c819fe 100644
--- a/hw/i386/intel_iommu_internal.h
+++ b/hw/i386/intel_iommu_internal.h
@@ -412,9 +412,7 @@  typedef union VTDInvDesc VTDInvDesc;
 /* Rsvd field masks for spte */
 #define VTD_SPTE_SNP 0x800ULL
 
-#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw, dt_supported) \
-        dt_supported ? \
-        (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
+#define VTD_SPTE_PAGE_L1_RSVD_MASK(aw) \
         (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 #define VTD_SPTE_PAGE_L2_RSVD_MASK(aw) \
         (0x800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
@@ -423,13 +421,9 @@  typedef union VTDInvDesc VTDInvDesc;
 #define VTD_SPTE_PAGE_L4_RSVD_MASK(aw) \
         (0x880ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 
-#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw, dt_supported) \
-        dt_supported ? \
-        (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
+#define VTD_SPTE_LPAGE_L2_RSVD_MASK(aw) \
         (0x1ff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
-#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw, dt_supported) \
-        dt_supported ? \
-        (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM | VTD_SL_TM)) : \
+#define VTD_SPTE_LPAGE_L3_RSVD_MASK(aw) \
         (0x3ffff800ULL | ~(VTD_HAW_MASK(aw) | VTD_SL_IGN_COM))
 
 /* Information about page-selective IOTLB invalidate */
@@ -536,6 +530,5 @@  typedef struct VTDRootEntry VTDRootEntry;
 #define VTD_SL_W                    (1ULL << 1)
 #define VTD_SL_PT_BASE_ADDR_MASK(aw) (~(VTD_PAGE_SIZE - 1) & VTD_HAW_MASK(aw))
 #define VTD_SL_IGN_COM              0xbff0000000000000ULL
-#define VTD_SL_TM                   (1ULL << 62)
 
 #endif
diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c
index 08fe218935..eb5aa2b2d5 100644
--- a/hw/i386/intel_iommu.c
+++ b/hw/i386/intel_iommu.c
@@ -4111,8 +4111,6 @@  static void vtd_cap_init(IntelIOMMUState *s)
  */
 static void vtd_init(IntelIOMMUState *s)
 {
-    X86IOMMUState *x86_iommu = X86_IOMMU_DEVICE(s);
-
     memset(s->csr, 0, DMAR_REG_SIZE);
     memset(s->wmask, 0, DMAR_REG_SIZE);
     memset(s->w1cmask, 0, DMAR_REG_SIZE);
@@ -4137,16 +4135,13 @@  static void vtd_init(IntelIOMMUState *s)
      * Rsvd field masks for spte
      */
     vtd_spte_rsvd[0] = ~0ULL;
-    vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits,
-                                                  x86_iommu->dt_supported);
+    vtd_spte_rsvd[1] = VTD_SPTE_PAGE_L1_RSVD_MASK(s->aw_bits);
     vtd_spte_rsvd[2] = VTD_SPTE_PAGE_L2_RSVD_MASK(s->aw_bits);
     vtd_spte_rsvd[3] = VTD_SPTE_PAGE_L3_RSVD_MASK(s->aw_bits);
     vtd_spte_rsvd[4] = VTD_SPTE_PAGE_L4_RSVD_MASK(s->aw_bits);
 
-    vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits,
-                                                    x86_iommu->dt_supported);
-    vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits,
-                                                    x86_iommu->dt_supported);
+    vtd_spte_rsvd_large[2] = VTD_SPTE_LPAGE_L2_RSVD_MASK(s->aw_bits);
+    vtd_spte_rsvd_large[3] = VTD_SPTE_LPAGE_L3_RSVD_MASK(s->aw_bits);
 
     if (s->scalable_mode || s->snoop_control) {
         vtd_spte_rsvd[1] &= ~VTD_SPTE_SNP;