| Message ID | 84264d0713fb51ae2b9b731e28fc14681beea853.1727345965.git.dsimic@manjaro.org (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | arm64: dts: rockchip: Move L3 cache outside CPUs in RK3588(S) SoC dtsi | expand |
On Thu, 26 Sep 2024 12:29:13 +0200, Dragan Simic wrote: > Move the "l3_cache" node outside the "cpus" node in the base dtsi file for > Rockchip RK3588(S) SoCs. The A55 and A76 CPU cores in these SoCs belong to > the ARM DynamIQ IP core lineup, which places the L3 cache outside the CPUs > and into the DynamIQ Shared Unit (DSU). [1] Thus, moving the L3 cache DT > node one level higher in the DT improves the way the physical topology of > the RK3588(S) SoCs is represented in the SoC dtsi files. > > [...] Applied, thanks! [1/1] arm64: dts: rockchip: Move L3 cache outside CPUs in RK3588(S) SoC dtsi commit: df5f6f2f62b9b50cef78f32909485b00fc7cf7f2 Best regards,
diff --git a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi index b6e4df180f0b..48a79b4b1b6e 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-base.dtsi @@ -337,15 +337,19 @@ l2_cache_b3: l2-cache-b3 { cache-unified; next-level-cache = <&l3_cache>; }; + }; - l3_cache: l3-cache { - compatible = "cache"; - cache-size = <3145728>; - cache-line-size = <64>; - cache-sets = <4096>; - cache-level = <3>; - cache-unified; - }; + /* + * The L3 cache belongs to the DynamIQ Shared Unit (DSU), + * so it's represented here, outside the "cpus" node + */ + l3_cache: l3-cache { + compatible = "cache"; + cache-size = <3145728>; + cache-line-size = <64>; + cache-sets = <4096>; + cache-level = <3>; + cache-unified; }; display_subsystem: display-subsystem {
Move the "l3_cache" node outside the "cpus" node in the base dtsi file for Rockchip RK3588(S) SoCs. The A55 and A76 CPU cores in these SoCs belong to the ARM DynamIQ IP core lineup, which places the L3 cache outside the CPUs and into the DynamIQ Shared Unit (DSU). [1] Thus, moving the L3 cache DT node one level higher in the DT improves the way the physical topology of the RK3588(S) SoCs is represented in the SoC dtsi files. While there, add a comment that explains it briefly, to save curious readers from the need to reference the repository log for a clarification. [1] ARM DynamIQ Shared Unit revision r4p0 TRM, version 0400-02 Fixes: c9211fa2602b ("arm64: dts: rockchip: Add base DT for rk3588 SoC") Helped-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Dragan Simic <dsimic@manjaro.org> --- Notes: See also a related discussion [2] that initiated this patch. [2] https://lore.kernel.org/linux-rockchip/2aa03ce3-1cca-4b3a-935d-6b1b68ebbb6e@arm.com/T/#u arch/arm64/boot/dts/rockchip/rk3588-base.dtsi | 20 +++++++++++-------- 1 file changed, 12 insertions(+), 8 deletions(-)