[v2] target/riscv/csr.c: Fix an access to VXSAT

Commit Message

Evgenii Prokopiev Sept. 26, 2024, 8:39 a.m. UTC

The register VXSAT should be RW only to the first bit.
The remaining bits should be 0.

The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture

The vxsat CSR has a single read-write least-significant bit (vxsat[0])
that indicates if a fixed-point instruction has had to saturate an output
value to fit into a destination format. Bits vxsat[XLEN-1:1]
should be written as zeros.

Signed-off-by: Evgenii Prokopiev <[e-mail]>
Reviewed-by: Daniel Henrique Barboza <[e-mail]>
---
Changes since v1: 
	- Added reviewed-by tag
 target/riscv/csr.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

Comments

Alistair Francis Oct. 2, 2024, 5:45 a.m. UTC | #1

On Thu, Sep 26, 2024 at 6:41 PM Evgenii Prokopiev
<[e-mail]> wrote:
>
> The register VXSAT should be RW only to the first bit.
> The remaining bits should be 0.
>
> The RISC-V Instruction Set Manual Volume I: Unprivileged Architecture
>
> The vxsat CSR has a single read-write least-significant bit (vxsat[0])
> that indicates if a fixed-point instruction has had to saturate an output
> value to fit into a destination format. Bits vxsat[XLEN-1:1]
> should be written as zeros.
>
> Signed-off-by: Evgenii Prokopiev <[e-mail]>
> Reviewed-by: Daniel Henrique Barboza <[e-mail]>

Reviewed-by: Alistair Francis <[e-mail]>

Alistair

> ---
> Changes since v1:
>         - Added reviewed-by tag
>  target/riscv/csr.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/target/riscv/csr.c b/target/riscv/csr.c
> index bd080f92b5..69c41212e9 100644
> --- a/target/riscv/csr.c
> +++ b/target/riscv/csr.c
> @@ -717,7 +717,7 @@ static RISCVException write_vxrm(CPURISCVState *env, int csrno,
>  static RISCVException read_vxsat(CPURISCVState *env, int csrno,
>                                   target_ulong *val)
>  {
> -    *val = env->vxsat;
> +    *val = env->vxsat & BIT(0);
>      return RISCV_EXCP_NONE;
>  }
>
> @@ -727,7 +727,7 @@ static RISCVException write_vxsat(CPURISCVState *env, int csrno,
>  #if !defined(CONFIG_USER_ONLY)
>      env->mstatus |= MSTATUS_VS;
>  #endif
> -    env->vxsat = val;
> +    env->vxsat = val & BIT(0);
>      return RISCV_EXCP_NONE;
>  }
>
> --
> 2.34.1
>
>

Patch

diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index bd080f92b5..69c41212e9 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -717,7 +717,7 @@  static RISCVException write_vxrm(CPURISCVState *env, int csrno,
 static RISCVException read_vxsat(CPURISCVState *env, int csrno,
                                  target_ulong *val)
 {
-    *val = env->vxsat;
+    *val = env->vxsat & BIT(0);
     return RISCV_EXCP_NONE;
 }
 
@@ -727,7 +727,7 @@  static RISCVException write_vxsat(CPURISCVState *env, int csrno,
 #if !defined(CONFIG_USER_ONLY)
     env->mstatus |= MSTATUS_VS;
 #endif
-    env->vxsat = val;
+    env->vxsat = val & BIT(0);
     return RISCV_EXCP_NONE;
 }