| Message ID | 20240908102018.3711527-10-avri.altman@wdc.com (mailing list archive) |
|---|---|
| State | New |
| Headers | show |
| Series | Add SDUC Support | expand |
On 9/8/24 11:20, Avri Altman wrote: > Prevent Host Software Queue from enabling for SDUC. In SDUC, CMD44 is > modified to include 6-bit upper address by utilizing its reserved bits. > Exclude hsq for SDUC for now. The message here is misleading, actually hsq has nothing to do with the actual CQ as in CMD44, it's just a hack to present itself to the mmc subsystem as such to then get more in-flight requests from mmc core, which can be prepared in advance and be issued asynchronously to the completion of the preceding request (in atomic context). So the card is completely oblivious to hsq. This is presumably broken though by the mandatory CMD22 for SDUC. > > Signed-off-by: Avri Altman <avri.altman@wdc.com> > --- > drivers/mmc/core/sd.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c > index 1d09f0f2e769..5d35fc8802c7 100644 > --- a/drivers/mmc/core/sd.c > +++ b/drivers/mmc/core/sd.c > @@ -1558,7 +1558,7 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr, > goto free_card; > } > > - if (host->cqe_ops && !host->cqe_enabled) { > + if (!mmc_card_ult_capacity(card) && host->cqe_ops && !host->cqe_enabled) { > err = host->cqe_ops->cqe_enable(host, card); > if (!err) { > host->cqe_enabled = true;
> On 9/8/24 11:20, Avri Altman wrote: > > Prevent Host Software Queue from enabling for SDUC. In SDUC, CMD44 is > > modified to include 6-bit upper address by utilizing its reserved bits. > > Exclude hsq for SDUC for now. > > The message here is misleading, actually hsq has nothing to do with the actual CQ > as in CMD44, it's just a hack to present itself to the mmc subsystem as such to > then get more in-flight requests from mmc core, which can be prepared in > advance and be issued asynchronously to the completion of the preceding > request (in atomic context). So the card is completely oblivious to hsq. > This is presumably broken though by the mandatory CMD22 for SDUC. Thanks. Somehow, I thought that hsq relies on hw command queue engine. If totally necessary, I will fix it in the next spin. Thanks, Avri > > > > > Signed-off-by: Avri Altman <avri.altman@wdc.com> > > --- > > drivers/mmc/core/sd.c | 2 +- > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index > > 1d09f0f2e769..5d35fc8802c7 100644 > > --- a/drivers/mmc/core/sd.c > > +++ b/drivers/mmc/core/sd.c > > @@ -1558,7 +1558,7 @@ static int mmc_sd_init_card(struct mmc_host *host, > u32 ocr, > > goto free_card; > > } > > > > - if (host->cqe_ops && !host->cqe_enabled) { > > + if (!mmc_card_ult_capacity(card) && host->cqe_ops && > > + !host->cqe_enabled) { > > err = host->cqe_ops->cqe_enable(host, card); > > if (!err) { > > host->cqe_enabled = true;
On Sun, 8 Sept 2024 at 14:11, Avri Altman <Avri.Altman@wdc.com> wrote: > > > On 9/8/24 11:20, Avri Altman wrote: > > > Prevent Host Software Queue from enabling for SDUC. In SDUC, CMD44 is > > > modified to include 6-bit upper address by utilizing its reserved bits. > > > Exclude hsq for SDUC for now. > > > > The message here is misleading, actually hsq has nothing to do with the actual CQ > > as in CMD44, it's just a hack to present itself to the mmc subsystem as such to > > then get more in-flight requests from mmc core, which can be prepared in > > advance and be issued asynchronously to the completion of the preceding > > request (in atomic context). So the card is completely oblivious to hsq. > > This is presumably broken though by the mandatory CMD22 for SDUC. > Thanks. > Somehow, I thought that hsq relies on hw command queue engine. > If totally necessary, I will fix it in the next spin. I suggest we at least update the commit message so we understand why we don't allow hsq for SDUC. It seems possible to make it work for hsq, but I don't mind if we consider that as an improvement on top of the initial support for SDUC. Does that make sense? [...] Kind regards Uffe
> On Sun, 8 Sept 2024 at 14:11, Avri Altman <Avri.Altman@wdc.com> wrote: > > > > > On 9/8/24 11:20, Avri Altman wrote: > > > > Prevent Host Software Queue from enabling for SDUC. In SDUC, CMD44 > > > > is modified to include 6-bit upper address by utilizing its reserved bits. > > > > Exclude hsq for SDUC for now. > > > > > > The message here is misleading, actually hsq has nothing to do with > > > the actual CQ as in CMD44, it's just a hack to present itself to the > > > mmc subsystem as such to then get more in-flight requests from mmc > > > core, which can be prepared in advance and be issued asynchronously > > > to the completion of the preceding request (in atomic context). So the > card is completely oblivious to hsq. > > > This is presumably broken though by the mandatory CMD22 for SDUC. > > Thanks. > > Somehow, I thought that hsq relies on hw command queue engine. > > If totally necessary, I will fix it in the next spin. > > I suggest we at least update the commit message so we understand why we > don't allow hsq for SDUC. It seems possible to make it work for hsq, but I > don't mind if we consider that as an improvement on top of the initial > support for SDUC. > > Does that make sense? Yes. Will do. Thanks, Avri > > [...] > > Kind regards > Uffe
diff --git a/drivers/mmc/core/sd.c b/drivers/mmc/core/sd.c index 1d09f0f2e769..5d35fc8802c7 100644 --- a/drivers/mmc/core/sd.c +++ b/drivers/mmc/core/sd.c @@ -1558,7 +1558,7 @@ static int mmc_sd_init_card(struct mmc_host *host, u32 ocr, goto free_card; } - if (host->cqe_ops && !host->cqe_enabled) { + if (!mmc_card_ult_capacity(card) && host->cqe_ops && !host->cqe_enabled) { err = host->cqe_ops->cqe_enable(host, card); if (!err) { host->cqe_enabled = true;
Prevent Host Software Queue from enabling for SDUC. In SDUC, CMD44 is modified to include 6-bit upper address by utilizing its reserved bits. Exclude hsq for SDUC for now. Signed-off-by: Avri Altman <avri.altman@wdc.com> --- drivers/mmc/core/sd.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)