| Message ID | 20240930091101.40591-9-philmd@linaro.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | target/mips: Remove target-specific endianness knowledge | expand |
On 9/30/24 02:10, Philippe Mathieu-Daudé wrote: > Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0. > > Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> > --- > target/mips/cpu.h | 3 +++ > target/mips/cpu.c | 9 ++++++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/target/mips/cpu.h b/target/mips/cpu.h > index 3e906a175a..070e11fe0d 100644 > --- a/target/mips/cpu.h > +++ b/target/mips/cpu.h > @@ -1209,6 +1209,9 @@ struct ArchCPU { > > Clock *clock; > Clock *count_div; /* Divider for CP0_Count clock */ > + > + /* Properties */ > + bool is_big_endian; > }; > > /** > diff --git a/target/mips/cpu.c b/target/mips/cpu.c > index 89655b1900..982f5bb4e2 100644 > --- a/target/mips/cpu.c > +++ b/target/mips/cpu.c > @@ -200,7 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type) > > /* Reset registers to their default values */ > env->CP0_PRid = env->cpu_model->CP0_PRid; > - env->CP0_Config0 = env->cpu_model->CP0_Config0; > + env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, > + CP0C0_BE, 1, cpu->is_big_endian); > #if TARGET_BIG_ENDIAN > env->CP0_Config0 |= (1 << CP0C0_BE); > #endif Missed removing this ifdef. r~
diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 3e906a175a..070e11fe0d 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1209,6 +1209,9 @@ struct ArchCPU { Clock *clock; Clock *count_div; /* Divider for CP0_Count clock */ + + /* Properties */ + bool is_big_endian; }; /** diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 89655b1900..982f5bb4e2 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -200,7 +200,8 @@ static void mips_cpu_reset_hold(Object *obj, ResetType type) /* Reset registers to their default values */ env->CP0_PRid = env->cpu_model->CP0_PRid; - env->CP0_Config0 = env->cpu_model->CP0_Config0; + env->CP0_Config0 = deposit32(env->cpu_model->CP0_Config0, + CP0C0_BE, 1, cpu->is_big_endian); #if TARGET_BIG_ENDIAN env->CP0_Config0 |= (1 << CP0C0_BE); #endif @@ -541,6 +542,11 @@ static const struct SysemuCPUOps mips_sysemu_ops = { }; #endif +static Property mips_cpu_properties[] = { + DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN), + DEFINE_PROP_END_OF_LIST(), +}; + #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" /* @@ -571,6 +577,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) DeviceClass *dc = DEVICE_CLASS(c); ResettableClass *rc = RESETTABLE_CLASS(c); + device_class_set_props(dc, mips_cpu_properties); device_class_set_parent_realize(dc, mips_cpu_realizefn, &mcc->parent_realize); resettable_class_set_parent_phases(rc, NULL, mips_cpu_reset_hold, NULL,
Add the "big-endian" property and set the CP0C0_BE bit in CP0_Config0. Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> --- target/mips/cpu.h | 3 +++ target/mips/cpu.c | 9 ++++++++- 2 files changed, 11 insertions(+), 1 deletion(-)